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Freescale Semiconductor Data Sheet: Advance Information
Document Number: MCIMX31 Rev. 2.3, 03/2007
MCIMX31 and MCIMX31L
i.MX31 and i.MX31L
Multimedia Applications Processors
Package Information Plastic Package Case 1581 14 x 14 mm, 0.5 mm Pitch
Ordering Information See Table 1 on page 3 for ordering information.
1
Introduction
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 1.2 Ordering Information . . . . . . . . . . . . . . . . . . . .3 1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .4 2 Functional Description and Application Information 4 2.1 ARM11 Microprocessor Core . . . . . . . . . . . . . .4 2.2 Module Inventory . . . . . . . . . . . . . . . . . . . . . . .6 3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . .9 4 Electrical Characteristics . . . . . . . . . . . . . . . . .10 4.1 i.MX31 and i.MX31L Chip-Level Conditions . .10 4.2 Supply Power-Up/Power-Down Requirements and Restrictions 14 4.3 Module-Level Electrical Specifications . . . . . .16 5 Package Information and Pinout . . . . . . . . . . .98 5.1 MAPBGA Production Package . . . . . . . . . . . .98 6 Product Documentation . . . . . . . . . . . . . . . . . .105 6.1 Revision History . . . . . . . . . . . . . . . . . . . . . .106
The i.MX31 (MCIMX31) and i.MX31L (MCIMX31L) are multimedia applications processors that represent the next step in low-power, high-performance application processors. Unless otherwise specified, the material in this data sheet is applicable to both the i.MX31 and i.MX31L processors. The i.MX31L does not include a graphics processing unit (GPU). Based on an ARM11TM microprocessor core, the i.MX31 and i.MX31L provide the performance with low power consumption required by modern digital devices such as: * Feature-rich cellular phones * Portable media players and mobile gaming machines * Personal digital assistants (PDAs) and Wireless PDAs * Portable DVD players * Digital cameras The i.MX31 and i.MX31L take advantage of the ARM1136JF-STM core running at overdrive speeds of 532 MHz, and are optimized for minimal power
This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2005, 2006, 2007. All rights reserved.
Introduction
consumption using the most advanced techniques for power saving (DPTC, DVFS, power gating, clock gating). With 90 nm technology and dual-Vt transistors (two threshold voltages), the i.MX31 and i.MX31L provide the optimal performance versus leakage current balance. The performance of the i.MX31 and i.MX31L is boosted by a multi-level cache system, and features peripheral devices such as an MPEG-4 Hardware Encoder (VGA, 30 fps), an Autonomous Image Processing Unit, a Vector Floating Point (VFP11) co-processor, and a RISC-based SDMA controller. The i.MX31 and i.MX31L support connections to various types of external memories, such as DDR, NAND Flash, NOR Flash, SDRAM, and SRAM. The i.MX31 and i.MX31L can be connected to a variety of external devices using technology, such as high-speed USB2.0 OTG, ATA, MMC/SDIO, and compact flash.
1.1
Features
The i.MX31 and i.MX31L are designed for the high-tier and mid-tier smartphone markets. They provide low-power solutions for high-performance demanding multimedia and graphics applications. The i.MX31 and i.MX31L are built around the ARM11 MCU core and implemented in the 90 nm technology. The systems include the following features: * Multimedia and floating-point hardware acceleration supporting: -- MPEG-4 real-time encode of up to VGA at 30 fps -- MPEG-4 real-time video post-processing of up to VGA at 30 fps -- Video conference call of up to QCIF-30 fps (decoder in software), 128 kbps -- Video streaming (playback) of up to VGA-30 fps, 384 kbps -- 3D graphics and other applications acceleration with the ARM(R) tightly-coupled Vector Floating Point co-processor -- On-the-fly video processing that reduces system memory load (for example, the power-efficient viewfinder application with no involvement of either the memory system or the ARM CPU) * Advanced power management -- Dynamic voltage and frequency scaling -- Multiple clock and power domains -- Independent gating of power domains * Multiple communication and expansion ports including a fast parallel interface to an external graphic accelerator (supporting major graphic accelerator vendors)
i.MX31/i.MX31L Advance Information, Rev. 2.3 2 Freescale Semiconductor
Introduction
1.2
Ordering Information
Table 1. Ordering Information
Table 1 provides the ordering information for the i.MX31 and i.MX31L.
Part Number MCIMX31VKN5 MCIMX31LVKN5 MCIMX31VKN5B MCIMX31LVKN5B
1
Silicon Revision1, 2, 3 1.15 1.15 1.2 1.2
Device Marking 2L38W and 3L38W 2L38W and 3L38W M45G M45G
Operating Temperature Range (C) 0 to 70 0 to 70 0 to 70 0 to 70
Package4
14 x 14 mm, 0.5 mm pitch, MAPBGA-457, Case 1581
Information on reading the silicon revision register can be found in the IC Identification (IIM) chapter of the Reference Manual, document order number MCIMX31RM. 2 Errata and fix information of the various mask sets can be found in the Errata, document order number MCIMX31CE. 3 Changes in output buffer characteristics can be found in the I/O Setting Exceptions and Special Pad Descriptions table in Chapter 4 of the Reference Manual, document order number MCIMX31RM. 4 Case 1581 is RoHS compliant, lead-free, MSL = 3, and solders at 260C.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 3
Functional Description and Application Information
1.3
Block Diagram
SRAM, PSRAM, NOR Flash SDRAM DDR NAND Flash, SmartMedia Camera Sensor (2) Parallel Display (2) Serial LCD
Figure 1 shows the i.MX31 and i.MX31L simplified interface block diagram.
Tamper Detection
Mouse Keyboard External Memory Interface (EMI) MPEG-4 Video Encoder Image Processing Unit (IPU) Inversion and Rotation Camera Interface Blending SDMA Display/TV Ctl Pre & Post Processing Internal Memory Expansion SDHC (2) PCMCIA/CF Mem Stick (2) SIM ATA Debug ECT SJC Security SCC RTIC RNGA GPS * GPU unavailable for i.MX31L ATA Hard Drive Timers RTC WDOG GPT EPIT (2) AP Peripherals AUDMUX SSI (2) UART (5) I2C (3) FIR CSPI (3) PWM USB Host (2) USB-OTG KPP GPIO CCM 1-WIRE(R) IIM GPU*
Power Management IC
ARM11TM Platform ARM1136JF-STM I-Cache D-Cache L2-Cache MAX ROMPATCH VFP
8x8 Keypad Serial EPROM
ETM
Fast IrDA
Bluetooth Baseband
WLAN
SD Card
PC Card
PC Card
USB Host/Device
Figure 1. i.MX31/i.MX31L Simplified Interface Block Diagram
2
2.1
Functional Description and Application Information
ARM11 Microprocessor Core
The CPU of the i.MX31 and i.MX31L is the ARM1136JF-S core based on the ARM v6 architecture. It supports the ARM Thumb(R) instruction sets, features Jazelle(R) technology (which enables direct execution of Java byte codes), and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers. The ARM1136JF-S processor core features: * Integer unit with integral EmbeddedICETM logic * Eight-stage pipeline * Branch prediction with return stack * Low-interrupt latency
i.MX31/i.MX31L Advance Information, Rev. 2.3 4 Freescale Semiconductor
Functional Description and Application Information
* * * * * * * *
Instruction and data memory management units (MMUs), managed using micro TLB structures backed by a unified main TLB Instruction and data L1 caches, including a non-blocking data cache with Hit-Under-Miss Virtually indexed/physically addressed L1 caches 64-bit interface to both L1 caches Write buffer (bypassable) High-speed Advanced Micro Bus Architecture (AMBA)TM L2 interface Vector Floating Point co-processor (VFP) for 3D graphics and other floating-point applications hardware acceleration ETMTM and JTAG-based debug support
2.1.1
Memory System
The ARM1136JF-S complex includes 16 KB Instruction and 16 KB Data L1 caches. It connects to the i.MX31 and i.MX31L L2 unified cache through 64-bit instruction (read-only), 64-bit data read/write (bi-directional), and 64-bit data write interfaces. The embedded 16K SRAM can be used for audio streaming data to avoid external memory accesses for the low-power audio playback, for security, or for other applications. There is also a 32-KB ROM for bootstrap code and other frequently-used code and data. A ROM patch module provides the ability to patch the internal ROM. It can also initiate an external boot by overriding the boot reset sequence by a jump to a configurable address. Table 2 shows information about the i.MX31 and i.MX31L core in tabular form.
Table 2. i.MX31/i.MX31L Core
Core Acronym Core Name Brief Description The ARM1136TM Platform consists of the ARM1136JF-S core, the ETM real-time debug modules, a 6 x 5 multi-layer AHB crossbar switch (MAX), and a Vector Floating Processor (VFP). The i.MX31/i.MX31L provide a high-performance ARM11 microprocessor core and highly integrated system functions. The ARM Application Processor (AP) and other subsystems address the needs of the personal, wireless, and portable product market with integrated peripherals, advanced processor core, and power management capabilities. Integrated Memory Includes * 16 Kbyte Instruction Cache * 16 Kbyte Data Cache * 128 Kbyte L2 Cache * 32 Kbyte ROM * 16 Kbyte RAM
ARM11 or ARM1136 ARM1136 Platform
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 5
Functional Description and Application Information
2.2
Module Inventory
Table 3 shows an alphabetical listing of the modules in the multimedia applications processor. For extended descriptions of the modules, see the reference manual. A cross-reference is provided to the electrical specifications and timing information for each module with external signal connections.
Table 3. Digital and Analog Modules
Block Mnemonic 1-Wire(R) ATA Block Name Functional Grouping Brief Description Section/ Page 4.3.4/19 4.3.5/21
1-Wire Interface Connectivity The 1-Wire module provides bi-directional communication between Peripheral the ARM11 core and external 1-Wire devices. Advanced Connectivity The ATA block is an AT attachment host interface. It is designed to Technology (AT) Peripheral interface with IDE hard disc drives and ATAPI optical disc drives. Attachment Digital Audio Multiplexer Clock Amplifier Module Clock Control Module Multimedia Peripheral Clock Clock The AUDMUX interconnections allow multiple, simultaneous audio/voice/data flows between the ports in point-to-point or point-to-multipoint configurations. The CAMP converts a square wave/sinusoidal input into a rail-to-rail square wave. The output of CAMP feeds the predivider. The CCM provides clock, reset, and power management control for the i.MX31 and i.MX31L.
AUDMUX
4.3.6/29
CAMP CCM CSPI
4.3.3/19 - 4.3.7/29
Configurable Connectivity The CSPI is equipped with data FIFOs and is a master/slave configurable serial peripheral interface module, capable of Serial Peripheral Peripheral interfacing to both SPI master and slave devices. Interface (x 3) Digital Phase Lock Loop Embedded Cross Trigger External Memory Interface Clock The DPLLs produce high-frequency on-chip clocks with low frequency and phase jitters. Note: External clock sources provide the reference frequencies. The ECT is composed of three CTIs (Cross Trigger Interface) and one CTM (Cross Trigger Matrix--key in the multi-core and multi-peripheral debug strategy. The EMI includes * Multi-Master Memory Interface (M3IF) * Enhanced SDRAM Controller (ESDCTL) * NAND Flash Controller (NFC) * Wireless External Interface Module (WEIM) The EPIT is a 32-bit "set and forget" timer which starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention.
DPLL
4.3.8/31
ECT
Debug
-
EMI
Memory Interface (EMI)
- 4.3.9.3/39, 4.3.9.1/32, 4.3.9.2/34 -
EPIT
Enhanced Periodic Interrupt Timer Embedded Trace Macrocell Fast InfraRed Interface
Timer Peripheral
ETM FIR
Debug/Trace The ETM (from ARM, Ltd.) supports real-time instruction and data tracing by way of ETM auxiliary I/O port. Connectivity This FIR is capable of establishing a 0.576 Mbit/s, 1.152 Mbit/s or 4 Peripheral Mbit/s half duplex link via a LED and IR detector. It supports 0.576 Mbit/s, 1.152 Mbit/s medium infrared (MIR) physical layer protocol and 4Mbit/s fast infrared (FIR) physical layer protocol defined by IrDA, version 1.4.
4.3.10/47 4.3.11/48
i.MX31/i.MX31L Advance Information, Rev. 2.3 6 Freescale Semiconductor
Functional Description and Application Information
Table 3. Digital and Analog Modules (continued)
Block Mnemonic Fusebox Block Name Fusebox Functional Grouping ROM Brief Description The Fusebox is a ROM that is factory configured by Freescale. Section/ Page 4.3.12/48 See also Table 9 -
GPIO
General Purpose I/O Module General Purpose Timer Graphics Processing Unit Inter IC Communication IC Identification Module Image Processing Unit Keypad Port
Pins
The GPIO provides several groups of 32-bit bidirectional, general purpose I/O. This peripheral provides dedicated general-purpose signals that can be configured as either inputs or outputs. The GPT is a multipurpose module used to measure intervals or generate periodic output. The GPU provides hardware acceleration for 2D and 3D graphics algorithms.
GPT GPU I2C
Timer Peripheral Multimedia Peripheral
- - 4.3.13/49
Connectivity The I2C provides serial interface for controlling the Sensor Interface Peripheral and other external devices. Data rates of up to 100 Kbits/s are supported. ID Multimedia Peripheral The IIM provides an interface for reading device identification. The IPU supports video and graphics processing functions in the i.MX31 and i.MX31L and interfaces to video, still image sensors, and displays.
IIM IPU
- 4.3.14/50, 4.3.15/52 -
KPP
Connectivity The KPP is used for keypad matrix scanning or as a general purpose Peripheral I/O. This peripheral simplifies the software task of scanning a keypad matrix. Multimedia Peripherals The MPEG-4 encoder accelerates video compression, following the MPEG-4 standard
MPEG-4 MSHC
MPEG-4 Video Encoder Memory Stick Host Controller Pads I/O PCM Pulse-Width Modulator Random Number Generator Accelerator
- 4.3.16/77
Connectivity The MSHC is placed in between the AIPS and the customer memory Peripheral stick to support data transfer from the i.MX31 or i.MX31L to the customer memory stick. Buffers and Drivers The PADIO serves as the interface between the internal modules and the device's external connections.
PADIO PCMCIA PWM RNGA
4.3.1/16 4.3.17/79 4.3.18/81 -
Connectivity The PCMCIA Host Adapter provides the control logic for PCMCIA Peripheral socket interfaces. Timer Peripheral Security The PWM has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The RNGA module is a digital integrated circuit capable of generating 32-bit random numbers. It is designed to comply with FIPS-140 standards for randomness and non-determinism. The RTC module provides a current stamp of seconds, minutes, hours, and days. Alarm and timer functions are also available for programming. The RTC supports dates from the year 1980 to 2050. The RTIC ensures the integrity of the peripheral memory contents and assists with boot authentication.
RTC
Real Time Clock Timer Peripheral Run-Time Integrity Checkers Security
-
RTIC
-
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 7
Functional Description and Application Information
Table 3. Digital and Analog Modules (continued)
Block Mnemonic SCC Block Name Security Controller Module Secured Digital Host Controller Functional Grouping Security Brief Description The SCC is a hardware component composed of two blocks--the Secure RAM module, and the Security Monitor. The Secure RAM provides a way of securely storing sensitive information. Section/ Page -
SDHC
Connectivity The SDHC controls the MMC (MultiMediaCard), SD (Secure Digital) Peripheral memory, and I/O cards by sending commands to cards and performing data accesses to and from the cards. The SDMA controller maximizes the system's performance by relieving the ARM core of the task of bulk data transfer from memory to memory or between memory and on-chip peripherals.
4.3.19/82
SDMA
Smart Direct System Memory Access Control Peripheral Subscriber Identification Module Secure JTAG Controller Synchronous Serial Interface
-
SIM
Connectivity The SIM interfaces to an external Subscriber Identification Card. It is Peripheral an asynchronous serial interface adapted for Smart Card communication for e-commerce applications. Debug The SJC provides debug and test control with maximum security and provides a flexible architecture for future derivatives or future multi-cores architecture. The SSI is a full-duplex, serial port that allows the device to communicate with a variety of serial devices, such as standard codecs, Digital Signal Processors (DSPs), microprocessors, peripherals, and popular industry audio codecs that implement the inter-IC sound bus standard (I2S) and Intel AC97 standard.
4.3.20/83
SJC
4.3.21/87
SSI
Multimedia Peripheral
4.3.22/89
UART
Universal Asynchronous Receiver/Trans mitter Universal Serial Bus-- 2 Host Controllers and 1 OTG (On-The-Go)
Connectivity The UART provides serial communication capability with external Peripheral devices through an RS-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception) or transforms electrical signals to signals that drive an infrared LED (for transmission) to provide low speed IrDA compatibility. Connectivity Peripherals * USB Host 1 is designed to support transceiverless connection to the on-board peripherals in Low Speed and Full Speed mode, and connection to the ULPI (UTMI+ Low-Pin Count) and Legacy Full Speed transceivers. * USB Host 2 is designed to support transceiverless connection to the Cellular Modem Baseband Processor. * The USB-OTG controller offers HS/FS/LS capabilities in Host mode and HS/FS in device mode. In Host mode, the controller supports direct connection of a FS/LS device (without external hub). In device (bypass) mode, the OTG port functions as gateway between the Host 1 Port and the OTG transceiver. The WDOG module protects against system failures by providing a method for the system to recover from unexpected events or programming errors.
-
USB
4.3.23/97
WDOG
Watchdog Timer Timer Module Peripheral
-
i.MX31/i.MX31L Advance Information, Rev. 2.3 8 Freescale Semiconductor
Signal Descriptions
3
Signal Descriptions
Signal descriptions are in the reference manual. Special signal considerations are listed following this paragraph. The BGA ball assignment is in Section 5, "Package Information and Pinout" on page 98. Special Signal Considerations: * Tamper detect (GPIO1_6) Tamper detect logic is used to issue a security violation. This logic is activated if the tamper detect input is asserted. The tamper detect logic is disabled after reset. After enabling the logic, it is impossible to disable it until the next reset. The GPR[16] bit functions as the tamper detect enable bit. GPIO1_6 functions similarly to other I/O with GPIO capabilities regardless of the status of the tamper detect enable bit. (For example, the GPIO1_6 can function as an input with GPIO capabilities, such as sampling through PSR or generating interrupts.) * Power ready (GPIO1_5) The power ready input, GPIO1_5, should be connected to an external power management IC power ready output signal. If not used, GPIO1_5 must either be (a) externally pulled-up to NVCC1 or (b) a no connect, internally pulled-up by enabling the on-chip pull-up resistor. GPIO1_5 is a dedicated input and cannot be used as a general-purpose input/output. * SJC_MOD SJC_MOD must be externally connected to GND for normal operation. Termination to GND through an external pull-down resistor (such as 1 k) is allowed, but the value should be much smaller than the on-chip 100 k pull-up. * CE_CONTROL CE_CONTROL is a reserved input and must be externally tied to GND through a 1 k resistor. * TTM_PAD TTM_PAD is for Freescale factory use only. Control bits indicate pull-up/down disabled. However, TTM_PAD is actually connected to an on-chip pull-down device. Users must either float this signal or tie it to GND. * M_REQUEST and M_GRANT These two signals are not utilized internally. The user should make no connection to these signals. * Clock Source Select (CLKSS) The CLKSS is the input that selects the default reference clock source providing input to the DPLL. To select CKIH, tie CLKSS to NVCC1. To select CKIL, tie CLKSS to ground. After initialization, the reference clock source can be changed (initial setting is overwritten) by programming the PRCS bits in the CCMR.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 9
Electrical Characteristics
4
Electrical Characteristics
This section provides the device-level and module-level electrical characteristics for the i.MX31 and i.MX31L.
4.1
i.MX31 and i.MX31L Chip-Level Conditions
This section provides the device-level electrical characteristics for the IC. See Table 4 for a quick reference to the individual tables and sections.
Table 4. i.MX31/i.MX31L Chip-Level Conditions
For these characteristics, ... Table 5, "Absolute Maximum Ratings" Table 7, "Operating Ranges" Table 8, "Interface Frequency" Section 4.1.1, "Supply Current Specifications" Section 4.2, "Supply Power-Up/Power-Down Requirements and Restrictions" Topic appears ... on page 10 on page 12 on page 13 on page 14 on page 14
CAUTION Stresses beyond those listed under "Table 5, "Absolute Maximum Ratings," on page 10 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under "Table 7, "Operating Ranges," on page 12 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Table 5. Absolute Maximum Ratings
Parameter Supply Voltage (Core) Supply Voltage (I/O) Input Voltage Range Storage Temperature ESD Damage Immunity: Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) Offset voltage allowed in run mode between core supplies.
1
Symbol QVCCmax NVCCmax VImax Tstorage
Min -0.5 -0.5 -0.5 -40
Max 1.65 3.3 NVCC +0.3 125
Units V V V
oC
Vesd
- - -
2000 200 500 15
V
Vcore_offset1
-
mV
The offset is the difference between all core voltage pair combinations of QVCC, QVCC1, and QVCC4.
i.MX31/i.MX31L Advance Information, Rev. 2.3 10 Freescale Semiconductor
Electrical Characteristics
Table 6 provides the thermal resistance data for the 14 x 14 mm, 0.5 mm pitch package.
Table 6. Thermal Resistance Data--14 x 14 mm Package
Rating Junction to Ambient (natural convection) Junction to Ambient (natural convection) Junction to Ambient (@200 ft/min) Junction to Ambient (@200 ft/min) Junction to Board Junction to Case Junction to Package Top (natural convection) Board Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) -- -- -- Symbol RJA RJA RJMA RJMA RJB RJC JT Value 56 30 46 26 17 10 2 Unit C/W C/W C/W C/W C/W C/W C/W Notes 1, 2, 3 1, 3 1, 2, 3 1, 3 1, 4 1, 5 1, 6
NOTES 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 11
Electrical Characteristics
Table 7 provides the operating ranges. NOTE The term NVCC in this section refers to the associated supply rail of an input or output. The association is shown in the Signal Multiplexing chapter of the reference manual. CAUTION NVCC6 and NVCC9 must be at the same voltage potential. These supplies are connected together on-chip to optimize ESD damage immunity.
Table 7. Operating Ranges
Symbol QVCC, QVCC1, QVCC4 Core Operating Voltage
1
Parameter 0 fARM 400 MHz, non-overdrive 0 fARM 400 MHz, overdrive2 0 fARM 532 MHz, overdrive2 State Retention Voltage3 I/O Supply Voltage, except DDR4 I/O Supply Voltage, DDR only non-overdrive overdrive5
Min 1.22 >1.47 1.55 0.95 1.75 >3.1 1.75
Max 1.47 1.65 1.65 - 3.1 3.3 1.95
Units
V
NVCC1, NVCC3-10 NVCC2, NVCC21, NVCC22
V V
FVCC, MVCC, PLL (Phase-Locked Loop) and FPM (Frequency Pre-multiplier) Supply Voltage6 non-overdrive SVCC, UVCC overdrive2 IOQVDD FUSE_VDD TA
1 2
V 1.3 >1.47 1.6 1.65 3.0 0 1.47 1.6 1.9 1.95 3.3 70 V V V
oC
On-device Level Shifter Supply Voltage Fusebox read Supply Voltage Fusebox write (program) Supply Voltage7 Operating Ambient Temperature Range
Measured at package balls, including peripherals, ARM, and L2 cache supplies (QVCC, QVCC1, QVCC4, respectively). Supply voltage is considered "overdrive" for voltages above 1.47 V. Operation time in overdrive--whether switching or not--must be limited to a cumulative duration of 1.25 years (10,950 hours) or less to sustain the maximum operating voltage without significant device degradation--for example, 25% (average 6 hours out of 24 yours per day) duty cycle for 5-year rated equipment. To tolerate the maximum operating overdrive voltage for 10 years, the device must have a duty cycle of 12.5% or less in overdrive (for example 3 out of 24 hours per day). Below 1.47V, duty cycle restrictions may apply for equipment rated above 5 years. 3 The SR voltage is applied to QVCC, QVCC1, and QVCC4 after the device is placed in SR mode. The Real-Time Clock (RTC) is operational in State Retention (SR) mode. 4 Overshoot and undershoot conditions (transitions above NVCC and below GND) on I/O must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. 5 Supply voltage is considered "overdrive" for voltages above 3.1 V. Operation time in overdrive--whether switching or not--must be limited to a cumulative duration of 1 year (8,760 hours) or less to sustain the maximum operating voltage without significant device degradation--for example, 20% (average 4.8 hours out of 24 hours per day) duty cycle for 5-year rated equipment. Operation at 3.3 V that exceeds a cumulative 3,504 hours may cause non-operation whenever supply voltage is reduced to 1.8 V; degradation may render the device too slow or inoperable. Below 3.1 V, duty cycle restrictions may apply for equipment rated above 5 years.
i.MX31/i.MX31L Advance Information, Rev. 2.3 12 Freescale Semiconductor
Electrical Characteristics For normal operating conditions, PLLs' and core supplies must maintain the following relation: PLL Core - 100 mV. In other words, for a 1.6 V core supply, PLL supplies must be set to 1.5 V or higher. PLL voltage must not be altered after power up, otherwise the PLL will be unstable and lose lock. To minimize inducing noise on the PLL supply line, source the voltage from a low-noise, dedicated supply. 7 Fuses might be inadvertently blown if written to while the voltage is below this minimum.
6
Table 8 provides information for interface frequency limits. For more details about clocks characteristics, see Section 4.3.8, "DPLL Electrical Specifications" on page 31 and Section 4.3.3, "Clock Amplifier Module (CAMP) Electrical Characteristics on page 19.
Table 8. Interface Frequency
ID 1 2 3
1
Parameter JTAG TCK Frequency CKIL Frequency1
Symbol fJTAG fCKIL fCKIH
Min DC 32 15
Typ 5 32.768 26
Max 10 38.4 75
Units MHz kHz MHz
CKIH Frequency2
CKIL must be driven by an external clock source to ensure proper start-up and operation of the device. CKIL is needed to clock the internal reset synchronizer, the watchdog, and the real-time clock. 2 DPTC functionality, specifically the voltage/frequency relation table, is dependent on CKIH frequency. At the time of publication, standard tables used by Freescale OSs provided for a CKIH frequency of 26 MHz only. Any deviation from this frequency requires an update to the OS. For more details, refer to the particular OS user's guide documentation.
Table 9 shows the fusebox supply current parameters.
Table 9. Fusebox Supply Current Parameters
Ref. Num 1 2 Description eFuse Program Current.1 Current to program one eFuse bit: efuse_pgm = 3.0V eFuse Read Current2 Current to read an 8-bit eFuse word vdd_fusebox = 1.875V Symbol Iprogram Iread Minimum - - Typical 35 5 Maximum 60 8 Units mA mA
1 2
The current Iprogram is during program time (tprogram). The current Iread is present for approximately 50 ns of the read access to the 8-bit word.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 13
Electrical Characteristics
4.1.1
Supply Current Specifications
Table 10. Current Consumption1, 2
QVCC (Peripheral) Typ Max - QVCC1 (ARM) Typ 0.5 Max - QVCC4 (L2) Typ - Max - FVCC + MVCC + SVCC + UVCC Unit (PLL) Typ 0.04 Max - mA
Table 10 shows the core current consumption for the i.MX31 and i.MX31L.
Mode
Conditions
State * QVCC and QVCC1 = 0.95 V Retention * L2 caches are power gated (QVCC4 = 0 V) * All PLLs are off, VCC = 1.4 V * ARM is in well bias * FPM is off * 32 kHz input is on * CKIH input is off * CAMP is off * TCK input is off * All modules are off * No external resistive loads * RNGA oscillator is off Wait * * * * * * * * * * * * QVCC,QVCC1, and QVCC4 = 1.22 V ARM is in wait for interrupt mode MAX is active L2 cache is stopped but powered MCU PLL is on (532 MHz), VCC = 1.4 V USB PLL and SPLL are off, VCC = 1.4 V FPM is on CKIH input is on CAMP is on 32 kHz input is on All clocks are gated off All modules are off (by programming CGR[2:0] registers) * RNGA oscillator is off * No external resistive loads
0.8
6.0
-
3.0
-
0.04
-
3.5
-
mA
1 2
Typical column: TA = 25C Maximum column: TA = 70C
4.2
Supply Power-Up/Power-Down Requirements and Restrictions
Any i.MX31/i.MX31L board design must comply with the power-up and power-down sequence guidelines as described in this section to guarantee reliable operation of the device. Any deviation from these sequences may result in any or all of the following situations: * Cause excessive current during power up phase. * Prevent the device from booting. * Cause irreversible damage to the i.MX31/i.MX31L (worst-case scenario).
i.MX31/i.MX31L Advance Information, Rev. 2.3 14 Freescale Semiconductor
Electrical Characteristics
4.2.1
Powering Up
The Power On Reset (POR) pin must be kept asserted (low) throughout the power up sequence. Power up logic must guarantee that all power sources reach their target values prior to the release (de-assertion) of POR. Figure 2 shows the power-up sequence. NOTE Stages need to be performed in the order shown; however, within each stage, supplies can be powered up in any order. For example, supplies IOQVDD, NVCC1, and NVCC3 through NVCC10 do not need to be powered up in the order shown. CAUTION NVCC6 and NVCC9 must be at the same voltage potential. These supplies are connected together on-chip to optimize ESD damage immunity.
Hold POR Asserted
1
Notes:
1 2 1 3
QVCC, QVCC1, QVCC4
The board design must guarantee that supplies reach 90% level before transition to the next state, using Power Management IC or other means. The NVCC1 supply must not precede IOQVDD by more than 0.2 V until IOQVDD has reached 1.5 V. If IOQVDD is powered up first, there are no restrictions. It is allowable for FVCC, MVCC, SVCC, and UVCC to be up after FUSE_VDD.
1, 2
IOQVDD, NVCC1, NVCC3-10
NVCC2, NVCC21, NVCC22
1
FUSE_VDD
1, 3
FVCC, MVCC, 1 SVCC, UVCC
Release POR
Figure 2. Power-Up Sequence
4.2.2
Powering Down
The power-down sequence should be completed as follows: 1. Lower the FUSE_VDD supply. 2. Lower the remaining supplies.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 15
Electrical Characteristics
4.3
Module-Level Electrical Specifications
This section contains the i.MX31 and i.MX31L electrical information including timing specifications, arranged in alphabetical order by module name.
4.3.1
I/O Pad (PADIO) Electrical Specifications
This section specifies the AC/DC characterization of functional I/O of the i.MX31. There are two main types of I/O: regular and DDR. In this document, the "Regular" type is referred to as GPIO.
4.3.1.1
DC Electrical Characteristics
The i.MX31/i.MX31L I/O parameters appear in Table 11 for GPIO. See Table 7, "Operating Ranges," on page 12 for temperature and supply voltage ranges. NOTE The term NVCC in this section refers to the associated supply rail of an input or output. The association is shown in the Signal Multiplexing chapter of the reference manual. NVCC for Table 11 refers to NVCC1 and NVCC3-10; QVCC refers to QVCC, QVCC1, and QVCC4.
Table 11. GPIO DC Electrical Parameters
Parameter High-level output voltage Symbol VOH Test Conditions IOH = -1 mA IOH = specified Drive Low-level output voltage VOL IOL = 1 mA IOL = specified Drive High-level output current, slow slew rate IOH_S VOH =0.8*NVCC Std Drive High Drive Max Drive VOH =0.8*NVCC Std Drive High Drive Max Drive VOL =0.2*NVCC Std Drive High Drive Max Drive VOL =0.2*NVCC Std Drive High Drive Max Drive - - Min NVCC -0.15 0.8*NVCC - - -2 -4 -8 - -4 -6 -8 - 2 4 8 - 4 6 8 0.7*NVCC 0 - - NVCC 0.3*QVCC V V - mA - mA - mA Typ - - - - - Max - - 0.15 0.2*NVCC - Units V V V V mA
High-level output current, fast slew rate
IOH_F
Low-level output current, slow slew rate
IOL_S
Low-level output current, fast slew rate
IOL_F
High-Level DC input voltage Low-Level DC input voltage
VIH VIL
i.MX31/i.MX31L Advance Information, Rev. 2.3 16 Freescale Semiconductor
Electrical Characteristics
Table 11. GPIO DC Electrical Parameters (continued)
Parameter Input Hysteresis Schmitt trigger VT+ Schmitt trigger VTPull-up resistor (100 k PU) Pull-down resistor (100 k PD) Input current (no PU/PD) Input current (100 k PU) Input current (100 k PD) Tri-state leakage current Symbol VHYS VT + VT RPU RPD IIN IIN IIN IOZ Test Conditions Hysteresis enabled Hysteresis enabled Hysteresis enabled - - VI = NVCC or GND VI = 0 VI = NVCC VI = 0 VI = NVCC VI = NVCC or GND I/O = High Z Min 0.25 0.5*QVCC - - - - - - - Typ - - - 100 100 - - - - Max - - 0.5*QVCC - - 1 25 0.1 0.25 28 2 A A A A A A Units V V V k
The i.MX31/i.MX31L I/O parameters appear in Table 12 for DDR (Double Data Rate). See Table 7, "Operating Ranges," on page 12 for temperature and supply voltage ranges. NOTE NVCC for Table 12 refers to NVCC2, NVCC21, and NVCC22.
Table 12. DDR (Double Data Rate) I/O DC Electrical Parameters
Parameter High-level output voltage Symbol VOH VOL IOH Test Conditions IOH = -1 mA IOH = specified Drive Low-level output voltage IOL = 1 mA IOL = specified Drive High-level output current VOH =0.8*NVCC Std Drive High Drive Max Drive DDR Drive1 VOL=0.2*NVCC Std Drive High Drive Max Drive DDR Drive1 - - VI = NVCC or GND I/O = High Z Min NVCC -0.12 0.8*NVCC - - -3.6 -7.2 -10.8 -14.4 - 3.6 7.2 10.8 14.4 0.7*NVCC -0.3 - NVCC NVCC+0.3 0 - 0.3*NVCC 2 V V A - mA Typ - - - - - Max - - 0.08 0.2*NVCC - Units V V V V mA
Low-level output current
IOL
High-Level DC input voltage Low-Level DC input voltage Tri-state leakage current
VIH VIL IOZ
1
Use of DDR Drive can result in excessive overshoot and ringing.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 17
Electrical Characteristics
4.3.2
AC Electrical Characteristics
Figure 3 depicts the load circuit for outputs. Figure 4 depicts the output transition time waveform. The range of operating conditions appears in Table 13 for slow general I/O, Table 14 for fast general I/O, and Table 15 for DDR I/O (unless otherwise noted).
From Output Under Test Test Point CL
CL includes package, probe and fixture capacitance
Figure 3. Load Circuit for Output
NVCC 80% 20% PA1 PA1 80% 20%
Output (at I/O)
0V
Figure 4. Output Transition Time Waveform Table 13. AC Electrical Characteristics of Slow1 General I/O
ID PA1 Parameter Output Transition Times (Max Drive) Output Transition Times (High Drive) Output Transition Times (Std Drive) Symbol tpr tpr tpr Test Condition 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min 0.92 1.5 1.52 2.75 2.79 5.39 Typ 1.95 2.98 - - Max 3.17 4.75 4.81 8.42 8.56 16.43 Units ns ns ns
1
Fast/slow characteristic is selected per GPIO (where available) by "slew rate" control. See reference manual.
Table 14. AC Electrical Characteristics of Fast1 General I/O 2
ID PA1 Parameter Output Transition Times (Max Drive) Output Transition Times (High Drive) Output Transition Times (Std Drive) Symbol tpr tpr tpr Test Condition 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min 0.68 1.34 .91 1.79 1.36 2.68 Typ 1.33 2.6 1.77 3.47 2.64 5.19 Max 2.07 4.06 2.74 5.41 4.12 8.11 Units ns ns ns
1 2
Fast/slow characteristic is selected per GPIO (where available) by "slew rate" control. See reference manual. Use of GPIO in fast mode with the associated NVCC > 1.95 V can result in excessive overshoot and ringing.
i.MX31/i.MX31L Advance Information, Rev. 2.3 18 Freescale Semiconductor
Electrical Characteristics
Table 15. AC Electrical Characteristics of DDR I/O
ID PA1 Parameter Output Transition Times (DDR Drive)1 Output Transition Times (Max Drive) Output Transition Times (High Drive) Output Transition Times (Std Drive) Symbol tpr tpr tpr tpr Test Condition 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min 0.51 0.97 0.67 1.29 .99 1.93 1.96 3.82 Typ 0.82 1.58 1.08 2.1 1.61 3.13 3.19 6.24 Max 1.28 2.46 1.69 3.27 2.51 4.89 4.99 9.73 Units ns ns ns ns
1
Use of DDR Drive can result in excessive overshoot and ringing.
4.3.3
Clock Amplifier Module (CAMP) Electrical Characteristics
This section outlines the Clock Amplifier Module (CAMP) specific electrical characteristics. Table 16 shows clock amplifier electrical characteristics.
Table 16. Clock Amplifier Electrical Characteristics for CKIH Input
Parameter Input Frequency VIL (for square wave input) VIH (for square wave input) Sinusoidal Input Amplitude Duty Cycle
1 2
Min 15 0 (VDD
1-
Typ - -
Max 75 0.3 3 VDD 55
Units MHz V V Vp-p %
0.25)
- - 50
0.4 2 45
VDD is the supply voltage of CAMP. See reference manual. This value of the sinusoidal input will be measured through characterization.
4.3.4
1-Wire Electrical Specifications
Figure 5 depicts the RPP timing, and Table 17 lists the RPP timing parameters.
OWIRE Tx "Reset Pulse" 1-Wire bus (BATT_LINE) DS2502 Tx "Presence Pulse" OW2
OW1
OW3 OW4
Figure 5. Reset and Presence Pulses (RPP) Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 19
Electrical Characteristics
Table 17. RPP Sequence Delay Comparisons Timing Parameters
ID OW1 OW2 OW3 OW4 Parameters Reset Time Low Presence Detect High Presence Detect Low Reset Time High Symbol tRSTL tPDH tPDL tRSTH Min 480 15 60 480 Typ 511 - - 512 Max - 60 240 - Units s s s s
Figure 6 depicts Write 0 Sequence timing, and Table 18 lists the timing parameters.
OW6 1-Wire bus (BATT_LINE)
OW5
Figure 6. Write 0 Sequence Timing Diagram Table 18. WR0 Sequence Timing Parameters
ID OW5 OW6 Parameter Write 0 Low Time Transmission Time Slot Symbol tWR0_low tSLOT Min 60 OW5 Typ 100 117 Max 120 120 Units s s
Figure 7 depicts Write 1 Sequence timing, Figure 8 depicts the Read Sequence timing, and Table 19 lists the timing parameters.
OW8 1-Wire bus (BATT_LINE)
OW7
Figure 7. Write 1 Sequence Timing Diagram
OW8 1-Wire bus (BATT_LINE)
OW7 OW9
Figure 8. Read Sequence Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 20 Freescale Semiconductor
Electrical Characteristics
Table 19. WR1/RD Timing Parameters
ID OW7 OW8 OW9 Parameter Write 1 / Read Low Time Transmission Time Slot Release Time Symbol tLOW1 tSLOT tRELEASE Min 1 60 15 Typ 5 117 - Max 15 120 45 Units s s s
4.3.5
ATA Electrical Specifications (ATA Bus, Bus Buffers)
This section discusses ATA parameters. For a detailed description, refer to the ATA specification. The user needs to use level shifters for 3.3 Volt or 5.0 Volt compatibility on the ATA interface. The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast UDMA mode operation is needed, this may not be compatible with bus buffers. Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus. According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals. When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus should drive from host to device. When its low, the bus should drive from device to host. Steering of the signal is such that contention on the host and device tri-state busses is always avoided.
4.3.5.1
Timing Parameters
In the timing equations, some timing parameters are used. These parameters depend on the implementation of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 20 shows ATA timing parameters.
Table 20. ATA Timing Parameters
Name T ti_ds Bus clock period (ipg_clk_ata) Set-up time ata_data to ata_iordy edge (UDMA-in only) UDMA0 UDMA1 UDMA2, UDMA3 UDMA4 UDMA5 ti_dh hold time ata_iordy edge to ata_data (UDMA-in only) UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 UDMA5 15 ns 10 ns 7 ns 5 ns 4 ns 5.0 ns 4.6 ns Description Value/ Contributing Factor1 peripheral clock frequency
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 21
Electrical Characteristics
Table 20. ATA Timing Parameters (continued)
Name tco Description propagation delay bus clock L-to-H to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en set-up time ata_data to bus clock L-to-H set-up time ata_iordy to bus clock H-to-L hold time ata_iordy to bus clock H to L Max difference in propagation delay bus clock L-to-H to any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en Max difference in buffer propagation delay for any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data (read) Max buffer propagation delay cable propagation delay for ata_data cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack Max difference in cable propagation delay between ata_iordy and ata_data (read) Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) Max difference in cable propagation delay without accounting for ground bounce Value/ Contributing Factor1 12.0 ns
tsu tsui thi tskew1
8.5 ns 8.5 ns 2.5 ns 7 ns
tskew2
transceiver
tskew3 tbuf tcable1 tcable2 tskew4 tskew5 tskew6
1
transceiver transceiver cable cable cable cable cable
Values provided where applicable.
4.3.5.2
PIO Mode Timing
Figure 9 shows timing for PIO read, and Table 21 lists the timing parameters for PIO read.
Figure 9. PIO Read Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 22 Freescale Semiconductor
Electrical Characteristics
Table 21. PIO Read Timing Parameters
ATA Parameter t1 t2 t9 t5 t6 tA trd Parameter from Figure 9 t1 t2r t9 t5 t6 tA trd1 Value t1 (min) = time_1 * T - (tskew1 + tskew2 + tskew5) t2 min) = time_2r * T - (tskew1 + tskew2 + tskew5) t9 (min) = time_9 * T - (tskew1 + tskew2 + tskew6) t5 (min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 0 tA (min) = (1.5 + time_ax) * T - (tco + tsui + tcable2 + tcable2 + 2*tbuf) trd1 (max) = (-trd) + (tskew3 + tskew4) trd1 (min) = (time_pio_rdx - 0.5)*T - (tsu + thi) (time_pio_rdx - 0.5) * T > tsu + thi + tskew3 + tskew4 t0 (min) = (time_1 + time_2 + time_9) * T Controlling Variable time_1 time_2r time_3 If not met, increase time_2 - time_ax time_pio_rdx
t0
-
time_1, time_2r, time_9
Figure 10 shows timing for PIO write, and Table 22 lists the timing parameters for PIO write.
Figure 10. Multiword DMA (MDMA) Timing Table 22. PIO Write Timing Parameters
ATA Parameter Parameter from Figure 10 t1 t2 t9 t3 t4 tA t1 t2w t9 - t4 tA Value t1 (min) = time_1 * T - (tskew1 + tskew2 + tskew5) t2 (min) = time_2w * T - (tskew1 + tskew2 + tskew5) t9 (min) = time_9 * T - (tskew1 + tskew2 + tskew6) t3 (min) = (time_2w - time_on)* T - (tskew1 + tskew2 +tskew5) t4 (min) = time_4 * T - tskew1 tA = (1.5 + time_ax) * T - (tco + tsui + tcable2 + tcable2 + 2*tbuf) Controlling Variable time_1 time_2w time_9 If not met, increase time_2w time_4 time_ax
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 23
Electrical Characteristics
Table 22. PIO Write Timing Parameters (continued)
ATA Parameter Parameter from Figure 10 t0 - - - - - Value t0(min) = (time_1 + time_2 + time_9) * T Avoid bus contention when switching buffer on by making ton long enough. Avoid bus contention when switching buffer off by making toff long enough. Controlling Variable time_1, time_2r, time_9 - -
Figure 11 shows timing for MDMA read, Figure 12 shows timing for MDMA write, and Table 23 lists the timing parameters for MDMA read and write.
Figure 11. MDMA Read Timing Diagram
Figure 12. MDMA Write Timing Diagram Table 23. MDMA Read and Write Timing Parameters
ATA Parameter tm, ti td tk Parameter from Figure 11, Figure 12 tm td, td1 tk Controlling Variable time_m time_d time_k
Value
tm (min) = ti (min) = time_m * T - (tskew1 + tskew2 + tskew5) td1.(min) = td (min) = time_d * T - (tskew1 + tskew2 + tskew6) tk.(min) = time_k * T - (tskew1 + tskew2 + tskew6)
i.MX31/i.MX31L Advance Information, Rev. 2.3 24 Freescale Semiconductor
Electrical Characteristics
Table 23. MDMA Read and Write Timing Parameters (continued)
ATA Parameter t0 tg(read) tf(read) tg(write) tf(write) tL tn, tj - Parameter from Figure 11, Figure 12 - tgr tfr - - - tkjn ton toff t0 (min) = (time_d + time_k) * T tgr (min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr.(min-drive) = td - te(drive) tfr (min-drive) = 0 tg (min-write) = time_d * T - (tskew1 + tskew2 + tskew5) tf (min-write) = time_k * T - (tskew1 + tskew2 + tskew6) tL (max) = (time_d + time_k-2)*T - (tsu + tco + 2*tbuf + 2*tcable2) tn= tj= tkjn = (max(time_k,. time_jn) * T - (tskew1 + tskew2 + tskew6) ton = time_on * T - tskew1 toff = time_off * T - tskew1 Controlling Variable time_d, time_k time_d - time_d time_k time_d, time_k time_jn -
Value
4.3.5.3
UDMA In Timing
Figure 13 shows timing when the UDMA in transfer starts, Figure 14 shows timing when the UDMA in host terminates transfer, Figure 15 shows timing when the UDMA in device terminates transfer, and Table 24 lists the timing parameters for UDMA in burst.
Figure 13. UDMA In Transfer Starts Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 25
Electrical Characteristics
Figure 14. UDMA In Host Terminates Transfer Timing Diagram
Figure 15. UDMA In Device Terminates Transfer Timing Diagram Table 24. UDMA In Burst Timing Parameters
Parameter from Figure 13, Figure 14, Figure 15 tack tenv tds1 tdh1
ATA Parameter
Description
Controlling Variable
tack tenv tds tdh
tack (min) = (time_ack * T) - (tskew1 + tskew2) tenv (min) = (time_env * T) - (tskew1 + tskew2) tenv (max) = (time_env * T) + (tskew1 + tskew2) tds - (tskew3) - ti_ds > 0 tdh - (tskew3) - ti_dh > 0
time_ack time_env tskew3, ti_ds, ti_dh should be low enough
i.MX31/i.MX31L Advance Information, Rev. 2.3 26 Freescale Semiconductor
Electrical Characteristics
Table 24. UDMA In Burst Timing Parameters (continued)
Parameter from Figure 13, Figure 14, Figure 15 tc1 trp tx11 tmli1 tzah tdzfs tcvh ton toff (tcyc - tskew) > T trp (min) = time_rp * T - (tskew1 + tskew2 + tskew6) (time_rp * T) - (tco + tsu + 3T + 2 *tbuf + 2*tcable2) > trfs (drive) tmli1 (min) = (time_mlix + 0.4) * T tzah (min) = (time_zah + 0.4) * T tdzfs = (time_dzfs * T) - (tskew1 + tskew2) tcvh = (time_cvh *T) - (tskew1 + tskew2) ton = time_on * T - tskew1 toff = time_off * T - tskew1
ATA Parameter
Description
Controlling Variable
tcyc trp - tmli tzah tdzfs tcvh -
T big enough time_rp time_rp time_mlix time_zah time_dzfs time_cvh -
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. 2. Make ton and toff big enough to avoid bus contention
1
4.3.5.4 UDMA Out Timing
Figure 16 shows timing when the UDMA out transfer starts, Figure 17 shows timing when the UDMA out host terminates transfer, Figure 18 shows timing when the UDMA out device terminates transfer, and Table 25 lists the timing parameters for UDMA out burst.
Figure 16. UDMA Out Transfer Starts Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 27
Electrical Characteristics
Figure 17. UDMA Out Host Terminates Transfer Timing Diagram
Figure 18. UDMA Out Device Terminates Transfer Timing Diagram Table 25. UDMA Out Burst Timing Parameters
Parameter from Figure 16, Figure 17, Figure 18 tack tenv tdvs tdvh tcyc -
ATA Parameter
Value
Controlling Variable
tack tenv tdvs tdvh tcyc t2cyc
tack (min) = (time_ack * T) - (tskew1 + tskew2) tenv (min) = (time_env * T) - (tskew1 + tskew2) tenv (max) = (time_env * T) + (tskew1 + tskew2) tdvs = (time_dvs * T) - (tskew1 + tskew2) tdvs = (time_dvh * T) - (tskew1 + tskew2) tcyc = time_cyc * T - (tskew1 + tskew2) t2cyc = time_cyc * 2 * T
time_ack time_env time_dvs time_dvh time_cyc time_cyc
i.MX31/i.MX31L Advance Information, Rev. 2.3 28 Freescale Semiconductor
Electrical Characteristics
Table 25. UDMA Out Burst Timing Parameters (continued)
Parameter from Figure 16, Figure 17, Figure 18 trfs tdzfs tss tdzfs_mli tli1 tli2 tli3 tcvh ton toff
ATA Parameter
Value
Controlling Variable
trfs1 - tss tmli tli tli tli tcvh -
trfs = 1.6 * T + tsui + tco + tbuf + tbuf tdzfs = time_dzfs * T - (tskew1) tss = time_ss * T - (tskew1 + tskew2) tdzfs_mli =max (time_dzfs, time_mli) * T - (tskew1 + tskew2) tli1 > 0 tli2 > 0 tli3 > 0 tcvh = (time_cvh *T) - (tskew1 + tskew2) ton = time_on * T - tskew1 toff = time_off * T - tskew1
- time_dzfs time_ss - - - - time_cvh -
4.3.6
AUDMUX Electrical Specifications
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSI) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is hence governed by the SSI module. Please refer to their respective electrical specifications.
4.3.7
CSPI Electrical Specifications
This section describes the electrical information of the CSPI.
4.3.7.1
CSPI Timing
Figure 19 and Figure 20 depict the master mode and slave mode timings of CSPI, and Table 26 lists the timing parameters.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 29
Electrical Characteristics
SPI_RDY
CS11
SSx
CS1
CS3
CS2 CS3
CS6 CS4
CS5
SCLK CS7 CS8 MOSI CS9 MISO CS10 CS2
Figure 19. CSPI Master Mode Timing Diagram
SSx
CS1
CS3
CS2 CS3
CS6 CS4
CS5
SCLK CS7 CS8 MISO CS9 MOSI CS10 CS2
Figure 20. CSPI Slave Mode Timing Diagram Table 26. CSPI Interface Timing Parameters
ID CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 CS11
1
Parameter SCLK Cycle Time SCLK High or Low Time SCLK Rise or Fall SSx pulse width SSx Lead Time (CS setup time) SSx Lag Time (CS hold time) Data Out Setup Time Data Out Hold Time Data In Setup Time Data In Hold Time SPI_RDY Setup Time
1
Symbol tclk tSW tRISE/FALL tCSLH tSCS tHCS tSmosi tHmosi tSmiso tHmiso tSDRY
Min 60 30 - 25 25 25 5 5 6 5 -
Max - - 7.6 - - - - - - - -
Units ns ns ns ns ns ns ns ns ns ns ns
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
i.MX31/i.MX31L Advance Information, Rev. 2.3 30 Freescale Semiconductor
Electrical Characteristics
4.3.8
DPLL Electrical Specifications
The three PLL's of the i.MX31/i.MX31L (MCU, USB, and Serial PLL) are all based on same DPLL design. The characteristics provided herein apply to all of them, except where noted explicitly. The PLL characteristics are provided based on measurements done for both sources--external clock source (CKIH), and FPM (Frequency Pre-Multiplier) source.
4.3.8.1
Electrical Specifications
Table 27. DPLL Specifications
Parameter Min 15 - 1 15 Typ 261 32; 32.768, 38.4 - - Max 752 - 16 35 Unit MHz Comments -
Table 27 lists the DPLL specification.
CKIH frequency CKIL frequency (Frequency Pre-multiplier (FPM) enable mode) Predivision factor (PD bits) PLL reference frequency range after Predivider PLL output frequency range:
kHz FPM lock time 480 s. - -
MHz 15 CKIH frequency/PD 35 MHz 15 FPM output/PD 35 MHz MHz ps - s - - Cycles of divided reference clock. In addition to the frequency
MPLL and SPLL 52 UPLL 190 Maximum allowed reference clock phase noise. Frequency lock time (FOL mode or non-integer MF) Phase lock time Maximum allowed PLL supply voltage ripple Maximum allowed PLL supply voltage ripple Maximum allowed PLL supply voltage ripple PLL output clock phase jitter PLL output clock period jitter
1
-
532 240
- - - - - - - -
- - - - - - - -
100
398 100 25 20 25 5.2 420
mV Fmodulation < 50 kHz mV 50 kHz < Fmodulation < 300 kHz mV Fmodulation > 300 kHz ns ps Measured on CLKO pin Measured on CLKO pin
The user or board designer must take into account that the use of a frequency other than 26 MHz would require adjustment to the DPTC-DVFS table, which is incorporated into operating system code. 2 The PLL reference frequency must be 35 MHz. Therefore, for frequencies between 35 MHz and 70 MHz, program the predivider to divide by 2 or more. If the CKIH frequency is above 70 MHz, program the predivider to 3 or more. For PD bit description, see the reference manual.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 31
Electrical Characteristics
4.3.9
EMI Electrical Specifications
This section provides electrical parametrics and timings for EMI module.
4.3.9.1
NAND Flash Controller Interface (NFC)
The NFC supports normal timing mode, using two flash clock cycles for one access of RE and WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 21, Figure 22, Figure 23, and Figure 24 depict the relative timing requirements among different signals of the NFC at module level, for normal mode, and Table 28 lists the timing parameters.
NFCLE NF1 NF3 NFCE NF5 NFWE NF6 NFALE NF8 NF9 NFIO[7:0] Command NF7 NF2 NF4
Figure 21. Command Latch Cycle Timing DIagram
NFCLE NF1 NF3 NFCE NF10 NF11 NF5 NFWE NF6 NFALE NF8 NF9 NFIO[7:0] Address NF7 NF4
Figure 22. Address Latch Cycle Timing DIagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 32 Freescale Semiconductor
Electrical Characteristics
NFCLE NF1 NF3 NFCE NF10 NF11 NF5 NFWE NF6 NFALE NF8 NF9 NFIO[15:0] Data to NF NF7
Figure 23. Write Data Latch Cycle Timing DIagram
NFCLE
NFCE NF14 NF15 NF13 NFRE NF16 NFRB NF12 NFIO[15:0] Data from NF NF17
Figure 24. Read Data Latch Cycle Timing DIagram Table 28. NFC Timing Parameters1
Timing T = NFC Clock Cycle2 Min NF1 NF2 NF3 NF4 NF5 NF6 NFCLE Setup Time NFCLE Hold Time NFCE Setup Time NFCE Hold Time NF_WP Pulse Width NFALE Setup Time tCLS tCLH tCS tCH tWP tALS T T-1.0 ns T-2.0 ns T-1.0 ns T-2.0 ns T-1.5 ns - 30 Max - - - - Example Timing for NFC Clock 33 MHz T = 30 ns Min 29 28 29 28 28.5 - Max - - - - ns ns ns ns ns ns
ID
Parameter
Symbol
Unit
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 33
Electrical Characteristics
Table 28. NFC Timing Parameters1 (continued)
Timing T = NFC Clock Cycle2 Min NF7 NF8 NF9 NFALE Hold Time Data Setup Time Data Hold Time tALH tDS tDH tWC tWH tRR tRP tRC tREH tDSR tDHR 6T 1.5T 2T T-3.0 ns T T-5.0 ns 2T T-2.5 ns - - - 0.5T-2.5 ns N/A N/A 180 45 60 12.5 10 0 Max - - - Example Timing for NFC Clock 33 MHz T = 30 ns Min 27 30 25 60 27.5 - - - - - - Max - - - ns ns ns ns ns ns ns ns ns ns ns
ID
Parameter
Symbol
Unit
NF10 Write Cycle Time NF11 NFWE Hold Time NF12 Ready to NFRE Low NF13 NFRE Pulse Width NF14 READ Cycle Time NF15 NFRE High Hold Time NF16 Data Setup on READ NF17 Data Hold on READ
1 2
The flash clock maximum frequency is 50 MHz. Subject to DPLL jitter specification on Table 27, "DPLL Specifications," on page 31.
NOTE High is defined as 80% of signal value and low is defined as 20% of signal value. NOTE Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is approximately 33 MHz (30 ns). All timings are listed according to this NFC clock frequency (multiples of NFC clock phases), except NF16 and NF17, which are not NFC clock related.
4.3.9.2
Wireless External Interface Module (WEIM)
All WEIM output control signals may be asserted and deasserted by internal clock related to BCLK rising edge or falling edge according to corresponding assertion/negation control fields. Address always begins related to BCLK falling edge but may be ended both on rising and falling edge in muxed mode according to control register configuration. Output data begins related to BCLK rising edge except in muxed mode where both rising and falling edge may be used according to control register configuration. Input data, ECB and DTACK all captured according to BCLK rising edge time. Figure 25 depicts the timing of the WEIM module, and Table 29 lists the timing parameters.
i.MX31/i.MX31L Advance Information, Rev. 2.3 34 Freescale Semiconductor
Electrical Characteristics WEIM Outputs Timing
WE22 WE21 BCLK WE1 Address CS[x] RW WE3 WE5 WE4 WE6 ... WE23 WE2
OE
WE7
WE8
EB[x]
WE9
WE10
WE11 LBA WE13 Output Data
WE12
WE14
WEIM Inputs Timing
BCLK WE16 Input Data WE15 WE18 ECB WE17 WE20 DTACK WE19
Figure 25. WEIM Bus Timing Diagram Table 29. WEIM Bus Timing Parameters
ID WE1 WE2 WE3 WE4 WE5 WE6 WE7 Clock fall to Address Valid Clock rise/fall to Address Invalid Clock rise/fall to CS[x] Valid Clock rise/fall to CS[x] Invalid Clock rise/fall to RW Valid Clock rise/fall to RW Invalid Clock rise/fall to OE Valid Parameter Min -0.5 -0.5 -3 -3 -3 -3 -3 Max 2.5 5 3 3 3 3 3 Unit ns ns ns ns ns ns ns
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 35
Electrical Characteristics
Table 29. WEIM Bus Timing Parameters (continued)
ID WE8 WE9 WE10 WE11 WE12 WE13 WE14 WE15 WE16 WE17 WE18 WE19 WE20 WE21 WE22 WE23
1 2
Parameter Clock rise/fall to OE Invalid Clock rise/fall to EB[x] Valid Clock rise/fall to EB[x] Invalid Clock rise/fall to LBA Valid Clock rise/fall to LBA Invalid Clock rise/fall to Output Data Valid Clock rise to Output Data Invalid Input Data Valid to Clock rise, FCE=0 FCE=1 Clock rise to Input Data Invalid, FCE=0 FCE=1 ECB setup time, FCE=0 FCE=1 ECB hold time, FCE=0 FCE=1 DTACK setup time1 DTACK hold time1 BCLK High Level Width2, 3 BCLK Low Level Width2, 3 BCLK Cycle time2
Min -3 -3 -3 -3 -3 - 2.5 - 2.5 8 2.5 -2 -2 6.5 3.5 -2 2 0 4.5 - - 15
Max 3 3 3 3 3 4 4 - - - - - - Tcycle/ 2-3 Tcycle/ 2-3 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Applies to rising edge timing BCLK parameters are being measured from the 50% VDD. 3 The actual cycle time is derived from the AHB bus clock frequency.
NOTE High is defined as 80% of signal value and low is defined as 20% of signal value. Test conditions: load capacitance, 25 pF. Recommended drive strength for all controls, address, and BCLK is Max drive. Figure 26, Figure 27, Figure 28, Figure 29, Figure 30, and Figure 31 depict some examples of basic WEIM accesses to external memory devices with the timing parameters mentioned in Table 29 for specific control parameter settings.
i.MX31/i.MX31L Advance Information, Rev. 2.3 36 Freescale Semiconductor
Electrical Characteristics
BCLK WE1 ADDR CS[x] RW WE11 LBA WE7 WE12 Last Valid Address WE3 V1 WE2 Next Address WE4
OE
WE8
EB[y]
WE9
WE10 WE16
DATA
V1 WE15
Figure 26. Asynchronous Memory Timing Diagram for Read Access--WSC=1
BCLK WE1 ADDR CS[x] Last Valid Address WE3 WE5 RW LBA OE WE9 WE10 WE14 DATA WE13 V1 WE11 WE12 V1 WE4 WE6 WE2 Next Address
EB[y]
Figure 27. Asynchronous Memory Timing Diagram for Write Access-- WSC=1, EBWA=1, EBWN=1, LBN=1
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 37
Electrical Characteristics
BCLK WE1 ADDR Last Valid Addr CS[x] RW WE11 WE12 WE8 WE3 Address V1 WE2 Address V2 WE4
LBA
OE EB[y]
WE7
WE9 WE18 WE18
WE10
ECB WE17 WE16 DATA WE15
V1 V1+2 Halfword Halfword
WE17 WE16
V2 Halfword V2+2 Halfword
WE15
Figure 28. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses-- WSC=2, SYNC=1, DOL=0
BCLK WE1 ADDR Last Valid Addr CS[x] WE3 Address V1
WE2
WE4
RW
WE5 WE11 WE12
WE6
LBA
OE EB[y] WE9 WE10
WE18 ECB WE17 WE14 DATA WE13 V1 WE13 WE14 V1+4 V1+8 V1+12
Figure 29. Synchronous Memory TIming Diagram for Burst Write Access-- BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1
i.MX31/i.MX31L Advance Information, Rev. 2.3 38 Freescale Semiconductor
Electrical Characteristics
WE1 ADDR/ Last Valid Addr M_DATA CS[x] WE3
BCLK
WE2 Address V1 WE13 Write Data
WE14 WE4
RW
WE5 Write WE11 WE12
WE6
LBA
OE EB[y] WE9 WE10
Figure 30. Muxed A/D Mode Timing Diagram for Asynchronous Write Access-- WSC=7, LBA=1, LBN=1, LAH=1
BCLK WE1 ADDR/ Last Valid Addr M_DATA WE3 CS[x] WE2 Address V1 WE16 Read Data WE15 WE4 RW WE11 LBA WE12
OE EB[y] WE9
WE7
WE8
WE10
Figure 31. Muxed A/D Mode Timing Diagram for Asynchronous Read Access-- WSC=7, LBA=1, LBN=1, LAH=1, OEA=7
4.3.9.3
ESDCTL Electrical Specifications
Figure 32, Figure 33, Figure 34, Figure 35, Figure 36, and Figure 37 depict the timings pertaining to the ESDCTL module, which interfaces Mobile DDR or SDR SDRAM. Table 30, Table 31, Table 32, Table 33, Table 34, and Table 35 list the timing parameters.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 39
Electrical Characteristics
SD1 SDCLK SDCLK SD4 CS SD5 RAS SD4 SD2 SD3
SD5 CAS SD4
SD4 SD5 WE SD6 SD7 ADDR ROW/BA
SD5
COL/BA SD8 SD10 SD9 Data
DQ
DQM
SD4
Note: CKE is high during the read/write cycle.
SD5
Figure 32. SDRAM Read Cycle Timing Diagram Table 30. DDR/SDR SDRAM Read Cycle Timing Parameters
ID SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 Parameter SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM, CKE setup time CS, RAS, CAS, WE, DQM, CKE hold time Address setup time Address hold time SDRAM access time Symbol tCH tCL tCK tCMS tCMH tAS tAH tAC Min 3.4 3.4 7.5 2.0 1.8 2.0 1.8 - Max 4.1 4.1 - - - - - 6.47 Unit ns ns ns ns ns ns ns ns
i.MX31/i.MX31L Advance Information, Rev. 2.3 40 Freescale Semiconductor
Electrical Characteristics
Table 30. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
ID SD9 SD10
1
Parameter Data out hold time1 Active to read/write command period
Symbol tOH tRC
Min 1.8 10
Max - -
Unit ns clock
Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see Table 34 and Table 35.
NOTE SDR SDRAM CLK parameters are being measured from the 50% point--that is, high is defined as 50% of signal value and low is defined as 50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz. NOTE The timing parameters are similar to the ones used in SDRAM data sheets--that is, Table 30 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 41
Electrical Characteristics
SD1 SDCLK SDCLK SD2 SD3 SD4 CS SD5 RAS SD11 CAS SD5 SD4 SD4
SD4
WE SD5 SD7 SD6 ADDR BA ROW / BA SD13 DQ DATA COL/BA SD12
SD5
SD14
DQM
Figure 33. SDR SDRAM Write Cycle Timing Diagram Table 31. SDR SDRAM Write Timing Parameters
ID SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD11 SD12 Parameter SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM, CKE setup time CS, RAS, CAS, WE, DQM, CKE hold time Address setup time Address hold time Precharge cycle period1 Active to read/write command delay1 Symbol tCH tCL tCK tCMS tCMH tAS tAH tRP tRCD Min 3.4 3.4 7.5 2.0 1.8 2.0 1.8 1 1 Max 4.1 4.1 - - - - - 4 8 Unit ns ns ns ns ns ns ns clock clock
i.MX31/i.MX31L Advance Information, Rev. 2.3 42 Freescale Semiconductor
Electrical Characteristics
Table 31. SDR SDRAM Write Timing Parameters (continued)
ID SD13 SD14
1
Parameter Data setup time Data hold time
Symbol tDS tDH
Min 2.0 1.3
Max - -
Unit ns ns
SD11 and SD12 are determined by SDRAM controller register settings.
NOTE SDR SDRAM CLK parameters are being measured from the 50% point--that is, high is defined as 50% of signal value and low is defined as 50% of signal value. NOTE The timing parameters are similar to the ones used in SDRAM data sheets--that is, Table 31 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency.
SD1 SDCLK SDCLK SD2 SD3 CS
RAS SD11 CAS SD10 WE SD10
SD7 SD6 ADDR BA ROW/BA
Figure 34. SDRAM Refresh Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 43
Electrical Characteristics
Table 32. SDRAM Refresh Timing Parameters
ID SD1 SD2 SD3 SD6 SD7 SD10 SD11
1
Parameter SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time Address setup time Address hold time Precharge cycle period1 Auto precharge command period1
Symbol tCH tCL tCK tAS tAH tRP tRC
Min 3.4 3.4 7.5 1.8 1.8 1 2
Max 4.1 4.1 - - - 4 20
Unit ns ns ns ns ns clock clock
SD10 and SD11 are determined by SDRAM controller register settings.
NOTE SDR SDRAM CLK parameters are being measured from the 50% point--that is, high is defined as 50% of signal value and low is defined as 50% of signal value. NOTE The timing parameters are similar to the ones used in SDRAM data sheets--that is, Table 32 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency.
i.MX31/i.MX31L Advance Information, Rev. 2.3 44 Freescale Semiconductor
Electrical Characteristics
SDCLK CS
RAS
CAS
WE
ADDR
BA
CKE
SD16
SD16
Don't care
Figure 35. SDRAM Self-Refresh Cycle Timing Diagram
NOTE The clock will continue to run unless both CKEs are low. Then the clock will be stopped in low state.
Table 33. SDRAM Self-Refresh Cycle Timing Parameters
ID SD16 Parameter CKE output delay time Symbol tCKS Min 1.8 Max - Unit ns
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 45
Electrical Characteristics
SDCLK SDCLK SD19 DQS (output) SD17 DQ (output) Data Data SD20
SD18
SD17 Data Data
SD18 Data Data Data Data
DQM (output) SD17
DM
DM
DM SD17
DM
DM SD18
DM
DM
DM
SD18
Figure 36. Mobile DDR SDRAM Write Cycle Timing Diagram Table 34. Mobile DDR SDRAM Write Cycle Timing Parameters1
ID SD17 SD18 SD19 SD20
1
Parameter DQ & DQM setup time to DQS DQ & DQM hold time to DQS Write cycle DQS falling edge to SDCLK output delay time. Write cycle DQS falling edge to SDCLK output hold time.
Symbol tDS tDH tDSS tDSH
Min 0.95 0.95 1.8 1.8
Max - - - -
Unit ns ns ns ns
Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.
NOTE SDRAM CLK and DQS related parameters are being measured from the 50% point--that is, high is defined as 50% of signal value and low is defined as 50% of signal value. NOTE The timing parameters are similar to the ones used in SDRAM data sheets--that is, Table 34 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency.
i.MX31/i.MX31L Advance Information, Rev. 2.3 46 Freescale Semiconductor
Electrical Characteristics
SDCLK SDCLK SD23 DQS (input) SD22 SD21 DQ (input) Data Data Data Data Data Data Data Data
Figure 37. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram Table 35. Mobile DDR SDRAM Read Cycle Timing Parameters
ID Parameter Symbol tDQSQ tQH tDQSCK Min Max Unit - 2.3 - 0.85 - 6.7 ns ns ns
SD21 DQS - DQ Skew (defines the Data valid window in read cycles related to DQS). SD22 DQS DQ HOLD time from DQS SD23 DQS output access time from SDCLK posedge
NOTE SDRAM CLK and DQS related parameters are being measured from the 50% point--that is, high is defined as 50% of signal value and low is defined as 50% of signal value. NOTE The timing parameters are similar to the ones used in SDRAM data sheets--that is, Table 35 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency.
4.3.10
ETM Electrical Specifications
ETM is an ARM protocol. The timing specifications in this section are given as a guide for a TPA that supports TRACECLK frequencies up to 133 MHz. Figure 38 depicts the TRACECLK timings of ETM, and Table 36 lists the timing parameters.
Figure 38. ETM TRACECLK Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 47
Electrical Characteristics
Table 36. ETM TRACECLK Timing Parameters
ID Tcyc Twl Twh Tr Tf Clock period Low pulse width High pulse width Clock and data rise time Clock and data fall time Parameter Min Frequency dependent 2 2 - - Max - - - 3 3 Unit ns ns ns ns ns
Figure 39 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and Table 37 lists the timing parameters.
Figure 39. Trace Data Timing Diagram Table 37. ETM Trace Data Timing Parameters
ID Ts Th Data setup Data hold Parameter Min 2 1 Max - - Unit ns ns
4.3.10.1
Half-Rate Clocking Mode
When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and falling edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 39.
4.3.11
FIR Electrical Specifications
FIR implements asynchronous infrared protocols (FIR, MIR) that are defined by IrDA(R) (Infrared Data Association). Refer to http://www.IrDA.org for details on FIR and MIR protocols.
4.3.12
Fusebox Electrical Specifications
Table 38. Fusebox Timing Characteristics
Ref. Num 1
1
Description Program time for eFuse1
Symbol tprogram
Minimum 125
Typical -
Maximum -
Units s
The program length is defined by the value defined in the epm_pgm_length[2:0] bits of the IIM module. The value to program is based on a 32 kHz clock source (4 * 1/32 kHz = 125 s)
i.MX31/i.MX31L Advance Information, Rev. 2.3 48 Freescale Semiconductor
Electrical Characteristics
4.3.13
I2C Electrical Specifications
This section describes the electrical information of the I2C Module.
4.3.13.1
I2C Module Timing
Figure 40 depicts the timing of I2C module. Table 39 lists the I2C module timing parameters where the I/O supply is 2.7 V. 1
I2DAT IC10 IC11 IC9
I2CLK
IC2
IC8
IC4
IC7
IC3
START
IC10 IC6 IC1 IC5
IC11
START
STOP
START
Figure 40. I2C Bus Timing Diagram Table 39. I2C Module Timing Parameters--I2C Pin I/O Supply=2.7 V
Standard Mode ID IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 IC12
1
Fast Mode Unit Min 2.5 0.6 0.6 Max - - - 0.92 - - - - -
4 4
Parameter Min I2CLK cycle time Hold time (repeated) START condition Set-up time for STOP condition Data hold time HIGH Period of I2CLK Clock LOW Period of the I2CLK Clock Set-up time for a repeated START condition Data set-up time Bus free time between a STOP and START condition Rise time of both I2DAT and I2CLK signals Fall time of both I2DAT and I2CLK signals Capacitive load for each bus line (Cb) 10 4.0 4.0 01 4.0 4.7 4.7 250 4.7 - - - Max - - - 3.45 - - - - - 1000 300 400
2
s s s s s s s ns s ns ns pF
01 0.6 1.3 0.6 1003 1.3 20+0.1Cb 20+0.1Cb -
300 300 400
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK. 2 The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal. 3 A Fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement of set-up time (ID IC7) of 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal. If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time (ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2CLK line is released. 4 Cb = total capacitance of one bus line in pF.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 49
Electrical Characteristics
4.3.14
4.3.14.1
IPU--Sensor Interfaces
Supported Camera Sensors
Table 40. Supported Camera Sensors1
Vendor Model CX11646, CX204902, CX204502 HDCP-2010, ADCS-10212, ADCS-10212 TC90A70 ICM202A, ICM1022 IM8801 TC5600, TC5600J, TC5640, TC5700, TC6000 MB86S02A MI-SOC-0133 MN39980 W6411, W6500, W65012, W66002, W65522, STV09742 OV7620, OV6630 LZ0P3714 (CCD) MC30300 (Python)2, SCM200142, SCM201142, SCM221142, SCM200272 LM96182
Table 40 lists the known supported camera sensors at the time of publication.
Conexant Agilant Toshiba ICMedia iMagic Transchip Fujitsu Micron Matsushita STMicro OmniVision Sharp Motorola National Semiconductor
1
Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only camera suppliers. 2 These sensors not validated at time of publication.
4.3.14.2
Functional Description
There are three timing modes supported by the IPU. 4.3.14.2.1 Pseudo BT.656 Video Mode
Smart camera sensors, which include imaging processing, usually support video mode transfer. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing syntax is defined by the BT.656 standard. This operation mode follows the recommendations of ITU BT.656 specifications. The only control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use.
i.MX31/i.MX31L Advance Information, Rev. 2.3 50 Freescale Semiconductor
Electrical Characteristics
4.3.14.2.2
Gated Clock Mode
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See Figure 41.
Start of Frame nth frame Active Line n+1th frame
SENSB_VSYNC
SENSB_HSYNC SENSB_PIX_CLK SENSB_DATA[9:0] invalid invalid
1st byte
1st byte
Figure 41. Gated Clock Mode Timing Diagram
A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the SENSB_VSYNC timing repeats. 4.3.14.2.3 Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in Section 4.3.14.2.2, "Gated Clock Mode" on page 51), except for the SENSB_HSYNC signal, which is not used. See Figure 42. All incoming pixel clocks are valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states low) until valid data is going to be transmitted over the bus.
Start of Frame nth frame n+1th frame
SENSB_VSYNC
SENSB_PIX_CLK SENSB_DATA[7:0] invalid invalid
1st byte
1st byte
Figure 42. Non-Gated Clock Mode Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 51
Electrical Characteristics
The timing described in Figure 42 is that of a Motorola sensor. Some other sensors may have a slightly different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC; active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
4.3.14.3
Electrical Characteristics
Figure 43 depicts the sensor interface timing, and Table 41 lists the timing parameters.
1/IP1
SENSB_MCLK (Sensor Input)
SENSB_PIX_CLK (Sensor Output) IP3 SENSB_DATA, SENSB_VSYNC, SENSB_HSYNC IP2
1/IP4
Figure 43. Sensor Interface Timing Diagram Table 41. Sensor Interface Timing Parameters
ID IP1 IP2 IP3 IP4 Parameter Sensor input clock frequency Data and control setup time Data and control holdup time Sensor output (pixel) clock frequency Symbol Fmck Tsu Thd Fpck Min. 0.01 5 3 0.01 Max. 133 - - 133 Units MHz ns ns MHz
4.3.15
4.3.15.1
IPU--Display Interfaces
Supported Display Components
Table 42 lists the known supported display components at the time of publication.
i.MX31/i.MX31L Advance Information, Rev. 2.3 52 Freescale Semiconductor
Electrical Characteristics
Table 42. Supported Display Components1
Type TFT displays (memory-less) Vendor Sharp (HR-TFT Super Mobile LCD family) Samsung (QCIF and QVGA TFT modules for mobile phones) Toshiba (LTM series) Model LQ035Q7 DB02, LM019LC1Sxx LTS180S1-HF1, LTS180S3-HF1, LTS350Q1-PE1, LTS350Q1-PD1, LTS220Q1-HE12 LTM022P8062, LTM04C380K2, LTM018A02A2, LTM020P3322, LTM021P3372, LTM019P3342, LTM022A7832, LTM022A05ZZ2 NL6448BC20-08E, NL8060BC31-27 S1D15xxx series, S1D19xxx series, S1D13713, S1D13715 SSD1301 (OLED), SSD1828 (LDCD) HD66766, HD66772 W2300 L1F10043 T2, L1F10044 T2, L1F10045 T2, L2D220022, L2D200142, L2F500322, L2D25001 T2 120 160 65K/4096 C-STN (#3284 LTD-1398-2) based on HD 66766 controller All displays with MPU 80/68K series interface and serial peripheral interface LM019LC1Sxx ACX506AKM ADV7174/7179 CS49xx series FS453/4
NEC Display controllers Epson Solomon Systech Hitachi ATI Smart display modules Epson Hitachi Densitron Europe LTD Sharp Sony Digital video encoders (for TV) Analog Devices Crystal (Cirrus Logic) Focus
1
Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only display component suppliers. 2 These display components not validated at time of publication.
4.3.15.2
4.3.15.2.1
Synchronous Interfaces
Interface to Active Matrix TFT LCD Panels, Functional Description
Figure 44 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with negative polarity. The sequence of events for active matrix interface timing is: * DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, DISPB_D3_CLK runs continuously. * DISPB_D3_HSYNC causes the panel to start a new line. * DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 53
Electrical Characteristics
*
DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off.
DISPB_D3_VSYNC DISPB_D3_HSYNC LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n
DISPB_D3_HSYNC
DISPB_D3_DRDY 1 DISPB_D3_CLK DISPB_D3_DATA 2 3 m-1 m
Figure 44. Interface Timing Diagram for TFT (Active Matrix) Panels
4.3.15.2.2
Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
Figure 45 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals.
IP7 IP9 IP8 Start of line IP5 IP6 IP10
DISPB_D3_CLK DISPB_D3_HSYNC DISPB_D3_DRDY
DISPB_D3_DATA
Figure 45. TFT Panels Timing Diagram--Horizontal Sync Pulse
Figure 46 depicts the vertical timing (timing of one frame). All figure parameters shown are programmable.
i.MX31/i.MX31L Advance Information, Rev. 2.3 54 Freescale Semiconductor
Electrical Characteristics
Start of frame IP13 DISPB_D3_VSYNC End of frame
DISPB_D3_HSYNC
DISPB_D3_DRDY
IP11
IP14 IP12
IP15
Figure 46. TFT Panels Timing Diagram--Vertical Sync Pulse
Table 43 shows timing parameters of signals presented in Figure 45 and Figure 46.
Table 43. Synchronous Display Interface Timing Parameters--Pixel Level
ID IP5 IP6 IP7 IP8 IP9 IP10 IP11 IP12 IP13 Parameter Display interface clock period Display pixel clock period Screen width HSYNC width Horizontal blank interval 1 Horizontal blank interval 2 HSYNC delay Screen height VSYNC width Symbol Tdicp Tdpcp Tsw Thsw Thbi1 Thbi2 Thsd Tsh Tvsw Tdicp1 (DISP3_IF_CLK_CNT_D+1) * Tdicp (SCREEN_WIDTH+1) * Tdpcp (H_SYNC_WIDTH+1) * Tdpcp BGXP * Tdpcp (SCREEN_WIDTH - BGXP - FW) * Tdpcp H_SYNC_DELAY * Tdpcp (SCREEN_HEIGHT+1) * Tsw if V_SYNC_WIDTH_L = 0 than (V_SYNC_WIDTH+1) * Tdpcp else (V_SYNC_WIDTH+1) * Tsw BGYP * Tsw (SCREEN_HEIGHT - BGYP - FH) * Tsw Value Units ns ns ns ns ns ns ns ns ns
IP14 IP15
1
Vertical blank interval 1 Vertical blank interval 2
Tvbi1 Tvbi2
ns ns
Display interface clock period immediate value. DISP3_IF_CLK_PER_WR for integer ----------------------------------------------------------------HSP_CLK_PERIOD DISP3_IF_CLK_PER_WR for fractional ----------------------------------------------------------------HSP_CLK_PERIOD
DISP3_IF_CLK_PER_WR T HSP_CLK ----------------------------------------------------------------- , HSP_CLK_PERIOD Tdicp = DISP3_IF_CLK_PER_WR T floor ----------------------------------------------------------------- + 0.5 0.5 , HSP_CLK HSP_CLK_PERIOD Display interface clock period average value.
DISP3_IF_CLK_PER_WR Tdicp = T HSP_CLK ----------------------------------------------------------------HSP_CLK_PERIOD
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 55
Electrical Characteristics
NOTE HSP_CLK is the High-Speed Port Clock, which is the input to the Image Processing Unit (IPU). Its frequency is controlled by the Clock Control Module (CCM) settings. The HSP_CLK frequency must be greater than or equal to the AHB clock frequency. The SCREEN_WIDTH, SCREEN_HEIGHT, H_SYNC_WIDTH, V_SYNC_WIDTH, BGXP, BGYP and V_SYNC_WIDTH_L parameters are programmed via the SDC_HOR_CONF, SDC_VER_CONF, SDC_BG_POS Registers. The FW and FH parameters are programmed for the corresponding DMA channel. The DISP3_IF_CLK_PER_WR, HSP_CLK_PERIOD and DISP3_IF_CLK_CNT_D parameters are programmed via the DI_DISP3_TIME_CONF, DI_HSP_CLK_PER and DI_DISP_ACC_CC Registers. Figure 47 depicts the synchronous display interface timing for access level, and Table 44 lists the timing parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the DI_DISP3_TIME_CONF Register.
DISPB_D3_VSYNC DISPB_D3_HSYNC DISPB_D3_DRDY other controls DISPB_D3_CLK IP20
IP16 DISPB_DATA
IP17
IP19
IP18
Figure 47. Synchronous Display Interface Timing Diagram--Access Level Table 44. Synchronous Display Interface Timing Parameters--Access Level
ID Parameter Symbol Tckl Tckh Tdsu Tdhd Tcsu Min Tdicd-Tdicu-1.5 Typ1 Tdicd2-Tdicu3 Max Tdicd-Tdicu+1.5 Units ns ns ns ns ns
IP16 Display interface clock low time IP17 Display interface clock high time IP18 Data setup time IP19 Data holdup time IP20 Control signals setup time to display interface clock
1
Tdicp-Tdicd+Tdicu-1.5 Tdicp-Tdicd+Tdicu Tdicp-Tdicd+Tdicu+1.5 Tdicd-3.5 Tdicp-Tdicd-3.5 Tdicd-3.5 Tdicu Tdicp-Tdicu Tdicu - - -
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific. 2 Display interface clock down time 1 2 DISP3_IF_CLK_DOWN_WR Tdicd = -- T HSP_CLK ceil -------------------------------------------------------------------------------2 HSP_CLK_PERIOD
i.MX31/i.MX31L Advance Information, Rev. 2.3 56 Freescale Semiconductor
Electrical Characteristics
3
Display interface clock up time 1 2 DISP3_IF_CLK_UP_WR Tdicu = -- T HSP_CLK ceil --------------------------------------------------------------------2 HSP_CLK_PERIOD
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
4.3.15.3
Interface to Sharp HR-TFT Panels
Figure 48 depicts the Sharp HR-TFT panel interface timing, and Table 45 lists the timing parameters. The CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY, REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to Section 4.3.15.2.2, "Interface to Active Matrix TFT LCD Panels, Electrical Characteristics" on page 54. The timing images correspond to straight polarity of the Sharp signals.
Horizontal timing
DISPB_D3_CLK
DISPB_D3_DATA
D1 D2
D320
DISPB_D3_SPL
IP21
1 DISPB_D3_CLK period
DISPB_D3_HSYNC IP23 IP22 DISPB_D3_CLS
IP24 DISPB_D3_PS
IP25 IP26 DISPB_D3_REV Example is drawn with FW+1=320 pixel/line, FH+1=240 lines. SPL pulse width is fixed and aligned to the first data of the line. REV toggles every HSYNC period.
Figure 48. Sharp HR-TFT Panel Interface Timing Diagram--Pixel Level
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 57
Electrical Characteristics
Table 45. Sharp Synchronous Display Interface Timing Parameters--Pixel Level
ID IP21 IP22 IP23 IP24 IP25 IP26 Parameter SPL rise time CLS rise time CLS fall time CLS rise and PS fall time PS rise time REV toggle time Symbol Tsplr Tclsr Tclsf Tpsf Tpsr Trev (BGXP - 1) * Tdpcp CLS_RISE_DELAY * Tdpcp CLS_FALL_DELAY * Tdpcp PS_FALL_DELAY * Tdpcp PS_RISE_DELAY * Tdpcp REV_TOGGLE_DELAY * Tdpcp Value Units ns ns ns ns ns ns
4.3.15.4
Synchronous Interface to Dual-Port Smart Displays
Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are identical to parameters of the synchronous interface. See Section 4.3.15.2.2, "Interface to Active Matrix TFT LCD Panels, Electrical Characteristics" on page 54. 4.3.15.4.1
Interface to a TV Encoder, Functional Description
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits D7-D0 of the value are mapped to bits LD17-LD10 of the data bus, respectively. Figure 49 depicts the interface timing, * The frequency of the clock DISPB_D3_CLK is 27 MHz (within 10%). * The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low. * The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal. It remains low for a single clock cycle. * The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC signal. It remains low for at least one clock cycle. -- At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC and DISPB_D3_HSYNC coincide. -- At a transition to an even field (of the same frame), they do not coincide. * The active intervals--during which data is transferred--are marked by the DISPB_D3_HSYNC signal being high.
i.MX31/i.MX31L Advance Information, Rev. 2.3 58 Freescale Semiconductor
Electrical Characteristics
DISPB_D3_CLK DISPB_D3_HSYNC DISPB_D3_VSYNC DISPB_D3_DRDY DISPB_DATA Cb Y Cr Y Cb Y Cr
Pixel Data Timing DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC 523 524 525 1 2 3 4 5 6 10
Even Field 261 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC 262 263 264 265 266 267
Odd Field 268 269 273
Odd Field
Even Field
Line and Field Timing - NTSC DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC Even Field 621 622 623 624 625 1 2 3 4 23
Odd Field
308 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC
309
310
311
312
313
314
315
316
336
Odd Field Line and Field Timing - PAL
Even Field
Figure 49. TV Encoder Interface Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 59
Electrical Characteristics
4.3.15.4.2
Interface to a TV Encoder, Electrical Characteristics
The timing characteristics of the TV encoder interface are identical to the synchronous display characteristics. See Section 4.3.15.2.2, "Interface to Active Matrix TFT LCD Panels, Electrical Characteristics" on page 54.
4.3.15.5
4.3.15.5.1
Asynchronous Interfaces Parallel Interfaces, Functional Description
The IPU supports the following asynchronous parallel interfaces: * System 80 interface -- Type 1 (sampling with the chip select signal) with and without byte enable signals. -- Type 2 (sampling with the read and write signals) with and without byte enable signals. * System 68k interface -- Type 1 (sampling with the chip select signal) with or without byte enable signals. -- Type 2 (sampling with the read and write signals) with or without byte enable signals. For each of four system interfaces, there are three burst modes: 1. Burst mode without a separate clock. The burst length is defined by the corresponding parameters of the IDMAC (when data is transferred from the system memory) of by the HBURST signal (when the MCU directly accesses the display via the slave AHB bus). For system 80 and system 68k type 1 interfaces, data is sampled by the CS signal and other control signals changes only when transfer direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD signals (system 80) or by the ENABLE signal (system 68k) and the CS signal stays active during the whole burst. 2. Burst mode with the separate clock DISPB_BCLK. In this mode, data is sampled with the DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are changed simultaneously with data when the bus state (read, write or wait) is altered. The CS signals and other controls move to non-active state after burst has been completed. 3. Single access mode. In this mode, slave AHB and DMA burst are broken to single accesses. The data is sampled with CS or other controls according the interface type as described above. All controls (including CS) become non-active for one display interface clock after each access. This mode corresponds to the ATI single access mode. Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 50, Figure 51, Figure 52, and Figure 53. These timing images correspond to active-low DISPB_D#_CS, DISPB_D#_WR and DISPB_D#_RD signals. Additionally, the IPU allows a programmable pause between two burst. The pause is defined in the HSP_CLK cycles. It allows to avoid timing violation between two sequential bursts or two accesses to different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.
i.MX31/i.MX31L Advance Information, Rev. 2.3 60 Freescale Semiconductor
Electrical Characteristics
DISPB_D#_CS
DISPB_PAR_RS DISPB_WR DISPB_RD
DISPB_DATA
Burst access mode with sampling by CS signal
DISPB_BCLK DISPB_D#_CS
DISPB_PAR_RS DISPB_WR DISPB_RD
DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS DISPB_WR DISPB_RD
DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 50. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 61
Electrical Characteristics
DISPB_D#_CS
DISPB_PAR_RS DISPB_WR DISPB_RD
DISPB_DATA
Burst access mode with sampling by WR/RD signals
DISPB_BCLK DISPB_D#_CS
DISPB_PAR_RS DISPB_WR DISPB_RD
DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS DISPB_WR DISPB_RD
DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 51. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 62 Freescale Semiconductor
Electrical Characteristics
DISPB_D#_CS
DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA
Burst access mode with sampling by CS signal
DISPB_BCLK DISPB_D#_CS
DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 52. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 63
Electrical Characteristics
DISPB_D#_CS
DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA
Burst access mode with sampling by ENABLE signal
DISPB_BCLK DISPB_D#_CS
DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 53. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram
Display read operation can be performed with wait states when each read access takes up to 4 display interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the DI_DISP0_TIME_CONF_3, DI_DISP1_TIME_CONF_3, DI_DISP2_TIME_CONF_3 Registers. Figure 54 shows timing of the parallel interface with read wait states.
i.MX31/i.MX31L Advance Information, Rev. 2.3 64 Freescale Semiconductor
Electrical Characteristics
WRITE OPERATION DISP0_RD_WAIT_ST=00 READ OPERATION
DISPB_D#_CS DISPB_RD DISPB_WR
DISPB_PAR_RS DISPB_DATA
DISP0_RD_WAIT_ST=01
DISPB_D#_CS DISPB_RD DISPB_WR
DISPB_PAR_RS DISPB_DATA
DISP0_RD_WAIT_ST=10 DISPB_D#_CS DISPB_RD DISPB_WR
DISPB_PAR_RS DISPB_DATA
Figure 54. Parallel Interface Timing Diagram--Read Wait States
4.3.15.5.2
Parallel Interfaces, Electrical Characteristics
Figure 55, Figure 57, Figure 56, and Figure 58 depict timing of asynchronous parallel interfaces based on the system 80 and system 68k interfaces. Table 46 lists the timing parameters at display access level. All timing images are based on active low control signals (signals polarity is controlled via the DI_DISP_SIG_POL Register).
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 65
Electrical Characteristics
IP28, IP27 DISPB_PAR_RS DISPB_RD (READ_L) DISPB_DATA[17] (READ_H) IP35, IP33 DISPB_D#_CS IP36, IP34
DISPB_WR (WRITE_L) DISPB_DATA[16] (WRITE_H) IP31, IP29 read point IP37 DISPB_DATA (Input) Read Data IP38 IP32, IP30
IP39 DISPB_DATA (Output)
IP40
IP46,IP44
IP47 IP45, IP43 IP42, IP41
Figure 55. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 66 Freescale Semiconductor
Electrical Characteristics
IP28, IP27 DISPB_PAR_RS DISPB_D#_CS
IP35, IP33 DISPB_RD (READ_L) DISPB_DATA[17] (READ_H) DISPB_WR (WRITE_L) DISPB_DATA[16] (WRITE_H) IP31, IP29 read point IP37 DISPB_DATA (Input) IP39 DISPB_DATA (Output) Read Data IP38
IP36, IP34
IP32, IP30
IP40
IP46,IP44 IP47 IP45, IP43 IP42, IP41
Figure 56. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 67
Electrical Characteristics
IP28, IP27
DISPB_PAR_RS DISPB_RD (ENABLE_L) DISPB_DATA[17] (ENABLE_H) IP35,IP33 DISPB_D#_CS IP36, IP34
DISPB_WR (READ/WRITE) IP31, IP29 read point IP37 DISPB_DATA (Input) IP39 DISPB_DATA (Output) Read Data IP38 IP32, IP30
IP40
IP46,IP44 IP47 IP45, IP43 IP42, IP41
Figure 57. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 68 Freescale Semiconductor
Electrical Characteristics
IP28, IP27 DISPB_PAR_RS DISPB_D#_CS
IP35,IP33 DISPB_RD (ENABLE_L) DISPB_DATA[17] (ENABLE_H) DISPB_WR (READ/WRITE) IP31, IP29 read point IP37 DISPB_DATA (Input) IP39 DISPB_DATA (Output) Read Data IP38
IP36, IP34
IP32, IP30
IP40
IP46,IP44 IP47 IP45, IP43 IP42, IP41
Figure 58. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram Table 46. Asynchronous Parallel Interface Timing Parameters--Access Level
ID Parameter Symbol Tcycr Tcycw Trl Trh Twl Twh Tdcsr Tdchr Tdcsw Tdicpr-1.5 Tdicpw-1.5 Tdicdr-Tdicur-1.5 Tdicpr-Tdicdr+Tdicur-1.5 Tdicdw-Tdicuw-1.5 Tdicpw-Tdicdw+ Tdicuw-1.5 Tdicur-1.5 Tdicpr-Tdicdr-1.5 Tdicuw-1.5 Min. Typ.1 Tdicpr2 Tdicpw
3
Max. Tdicpr+1.5 Tdicpw+1.5 Tdicdr-Tdicur+1.5 Tdicpr-Tdicdr+Tdicur+1.5
Units ns ns ns ns ns ns ns ns ns
IP27 Read system cycle time IP28 Write system cycle time IP29 Read low pulse width IP30 Read high pulse width IP31 Write low pulse width IP32 Write high pulse width IP33 Controls setup time for read IP34 Controls hold time for read IP35 Controls setup time for write
Tdicdr4-Tdicur5 Tdicpr-Tdicdr+ Tdicur
Tdicdw6-Tdicuw7 Tdicdw-Tdicuw+1.5 Tdicpw-Tdicdw+ Tdicuw Tdicur Tdicpr-Tdicdr Tdicuw Tdicpw-Tdicdw+ Tdicuw+1.5 - - -
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 69
Electrical Characteristics
Table 46. Asynchronous Parallel Interface Timing Parameters--Access Level (continued)
ID Parameter Symbol Tdchw Tracc
8
Min. Tdicpw-Tdicdw-1.5 0 Tdrp-Tlbd-Tdicdr+1.5 Tdicdw-1.5 Tdicpw-Tdicdw-1.5 Tdicpr-1.5
Typ.1 Tdicpw-Tdicdw - - Tdicdw Tdicpw-Tdicdw Tdicpr Tdicpw Tdicdr Tdicur Tdicdw Tdicuw Tdrp
9
Max. - Tdrp -Tlbd -Tdicur-1.5 Tdicpr-Tdicdr-1.5 - - Tdicpr+1.5 Tdicpw+1.5 Tdicdr+1.5 Tdicur+1.5 Tdicdw+1.5 Tdicuw+1.5 Tdrp+1.5
10
Units ns ns ns ns ns ns ns ns ns ns ns ns
IP36 Controls hold time for write IP37 Slave device data delay
8
IP38 Slave device data hold time IP39 Write data setup time IP40 Write data hold time IP41 Read period2
3
Troh Tds Tdh Tdicpr
IP42 Write period IP43 Read down
Tdicpw Tdicpw-1.5 Tdicdr Tdicur Tdicdr-1.5 Tdicur-1.5
5
time4 time6
IP44 Read up time IP45 Write down IP46 Write up
Tdicdw Tdicdw-1.5 Tdicuw Tdicuw-1.5 Tdrp Tdrp-1.5
time7 point9
IP47 Read time
1The
exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific. 2 Display interface clock period value for read:
DISP#_IF_CLK_PER_RD Tdicpr = T HSP_CLK ceil --------------------------------------------------------------HSP_CLK_PERIOD
3
Display interface clock period value for write:
DISP#_IF_CLK_PER_WR Tdicpw = T HSP_CLK ceil ----------------------------------------------------------------HSP_CLK_PERIOD
4
Display interface clock down time for read:
1 2 DISP#_IF_CLK_DOWN_RD Tdicdr = -- T HSP_CLK ceil ------------------------------------------------------------------------------2 HSP_CLK_PERIOD
5
Display interface clock up time for read:
1 2 DISP#_IF_CLK_UP_RD Tdicur = -- T HSP_CLK ceil -------------------------------------------------------------------2 HSP_CLK_PERIOD
6
Display interface clock down time for write:
1 2 DISP#_IF_CLK_DOWN_WR Tdicdw = -- T HSP_CLK ceil -------------------------------------------------------------------------------2 HSP_CLK_PERIOD
7
Display interface clock up time for write:
1 2 DISP#_IF_CLK_UP_WR Tdicuw = -- T HSP_CLK ceil --------------------------------------------------------------------2 HSP_CLK_PERIOD
8 9
This parameter is a requirement to the display connected to the IPU Data read point
DISP#_READ_EN Tdrp = T HSP_CLK ceil ------------------------------------------------HSP_CLK_PERIOD
10 Loopback
delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific.
i.MX31/i.MX31L Advance Information, Rev. 2.3 70 Freescale Semiconductor
Electrical Characteristics
The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD, DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD, DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers. 4.3.15.5.3
Serial Interfaces, Functional Description
The IPU supports the following types of asynchronous serial interfaces: * 3-wire (with bidirectional data line) * 4-wire (with separate data input and output lines) * 5-wire type 1 (with sampling RS by the serial clock) * 5-wire type 2 (with sampling RS by the chip select signal) Figure 59 depicts timing of the 3-wire serial interface. The timing images correspond to active-low DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal. For this interface, a bidirectional data line is used outside the device. The IPU still uses separate input and output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal provided by the IPU. Each data transfer can be preceded by an optional preamble with programmable length and contents. The preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is programmable. The RW bit can be disabled. The following data can consist of one word or of a whole burst. The interface parameters are controlled by the DI_SER_DISP1_CONF and DI_SER_DISP2_CONF Registers.
DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle
DISPB_SD_D_CLK DISPB_SD_D RW RS D7 D6 D5 D4 D3 D2 D1 D0
Preamble
Input or output data
Figure 59. 3-wire Serial Interface Timing Diagram
Figure 60 depicts timing of the 4-wire serial interface. For this interface, there are separate input and output data lines both inside and outside the device.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 71
Electrical Characteristics Write
DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle
DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) RW RS D7 D6 D5 D4 D3 D2 D1 D0
Output data
Read
DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle
DISPB_SD_D_CLK DISPB_SD_D (Output) RW RS
Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0
Input data
Figure 60. 4-wire Serial Interface Timing Diagram
Figure 61 depicts timing of the 5-wire serial interface (Type 1). For this interface, a separate RS line is added. When a burst is transmitted within single active chip select interval, the RS can be changed at boundaries of words.
i.MX31/i.MX31L Advance Information, Rev. 2.3 72 Freescale Semiconductor
Electrical Characteristics Write
DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle
DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) DISPB_SER_RS RW D7 D6 D5 D4 D3 D2 D1 D0
Output data
Read
DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle
DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 RW
Input data DISPB_SER_RS
Figure 61. 5-wire Serial Interface (Type 1) Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 73
Electrical Characteristics
Figure 62 depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is added. When a burst is transmitted within single active chip select interval, the RS can be changed at boundaries of words.
Write
DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle
DISPB_SD_D_CLK DISPB_SD_D (Output) RW D7 D6 D5 D4 D3 D2 D1 D0
Preamble DISPB_SD_D (Input) 1 display IF clock cycle
Output data
DISPB_SER_RS
Read
DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle
DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 RW
DISPB_SER_RS
1 display IF clock cycle
Input data
Figure 62. 5-wire Serial Interface (Type 2) Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 74 Freescale Semiconductor
Electrical Characteristics
4.3.15.5.4
Serial Interfaces, Electrical Characteristics
Figure 63 depicts timing of the serial interface. Table 47 lists the timing parameters at display access level.
IP49, IP48 DISPB_SER_RS
IP56,IP54
IP57, IP55
DISPB_SD_D_CLK
IP50, IP52 read point IP58 DISPB_DATA (Input) IP60 DISPB_DATA (Output) Read Data IP59
IP51, IP53
IP61
IP67,IP65 IP47 IP64, IP66 IP62, IP63
Figure 63. Asynchronous Serial Interface Timing Diagram Table 47. Asynchronous Serial Interface Timing Parameters--Access Level
ID Parameter Symbol Tcycr Tcycw Trl Trh Twl Twh Tdcsr Tdchr Tdicpr-1.5 Tdicpw-1.5 Tdicdr-Tdicur-1.5 Min. Typ.1 Tdicpr2 Tdicpw3 Tdicdr4-Tdicur5 Max. Tdicpr+1.5 Tdicpw+1.5 Tdicdr-Tdicur+1.5 Tdicpr-Tdicdr+Tdicur+1.5 Units ns ns ns ns ns ns ns ns
IP48 Read system cycle time IP49 Write system cycle time IP50 Read clock low pulse width IP51 Read clock high pulse width IP52 Write clock low pulse width IP53 Write clock high pulse width IP54 Controls setup time for read IP55 Controls hold time for read
Tdicpr-Tdicdr+Tdicur-1.5 Tdicpr-Tdicdr+ Tdicur Tdicdw-Tdicuw-1.5 Tdicpw-Tdicdw+ Tdicuw-1.5 Tdicur-1.5 Tdicpr-Tdicdr-1.5
Tdicdw6-Tdicuw7 Tdicdw-Tdicuw+1.5 Tdicpw-Tdicdw+ Tdicuw Tdicur Tdicpr-Tdicdr Tdicpw-Tdicdw+ Tdicuw+1.5 - -
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 75
Electrical Characteristics
Table 47. Asynchronous Serial Interface Timing Parameters--Access Level (continued)
ID Parameter Symbol Tdcsw Tdchw Tracc
8
Min. Tdicuw-1.5 Tdicpw-Tdicdw-1.5 0 Tdrp-Tlbd-Tdicdr+1.5 Tdicdw-1.5 Tdicpw-Tdicdw-1.5 Tdicpr-1.5
Typ.1 Tdicuw Tdicpw-Tdicdw - - Tdicdw Tdicpw-Tdicdw Tdicpr Tdicpw Tdicdr Tdicur Tdicdw Tdicuw Tdrp
9
Max. - - Tdrp -Tlbd -Tdicur-1.5 Tdicpr-Tdicdr-1.5 - - Tdicpr+1.5 Tdicpw+1.5 Tdicdr+1.5 Tdicur+1.5 Tdicdw+1.5 Tdicuw+1.5 Tdrp+1.5
10
Units ns ns ns ns ns ns ns ns ns ns ns ns ns
IP56 Controls setup time for write IP57 Controls hold time for write IP58 Slave device data delay
8
IP59 Slave device data hold time IP60 Write data setup time IP61 Write data hold time IP62 Read IP63 Write period2 period3
4
Troh Tds Tdh Tdicpr
Tdicpw Tdicpw-1.5 Tdicdr Tdicur Tdicdr-1.5 Tdicur-1.5
IP64 Read down time IP65 Read up time5
IP66 Write down IP67 Write up
time6
Tdicdw Tdicdw-1.5 Tdicuw Tdicuw-1.5 Tdrp Tdrp-1.5
time7 point9
IP68 Read time
1
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific. 2 Display interface clock period value for read:
DISP#_IF_CLK_PER_RD Tdicpr = T HSP_CLK ceil --------------------------------------------------------------HSP_CLK_PERIOD
3
Display interface clock period value for write:
DISP#_IF_CLK_PER_WR Tdicpw = T HSP_CLK ceil ----------------------------------------------------------------HSP_CLK_PERIOD
4
Display interface clock down time for read:
1 2 DISP#_IF_CLK_DOWN_RD Tdicdr = -- T HSP_CLK ceil ------------------------------------------------------------------------------2 HSP_CLK_PERIOD
5
Display interface clock up time for read:
1 2 DISP#_IF_CLK_UP_RD Tdicur = -- T ceil -------------------------------------------------------------------2 HSP_CLK HSP_CLK_PERIOD
6
Display interface clock down time for write:
1 2 DISP#_IF_CLK_DOWN_WR Tdicdw = -- T ceil -------------------------------------------------------------------------------2 HSP_CLK HSP_CLK_PERIOD
7
Display interface clock up time for write:
1 2 DISP#_IF_CLK_UP_WR Tdicuw = -- T HSP_CLK ceil --------------------------------------------------------------------2 HSP_CLK_PERIOD
8 9
This parameter is a requirement to the display connected to the IPU. Data read point:
HSP_CLK DISP#_READ_EN ceil ------------------------------------------------HSP_CLK_PERIOD
Tdrp = T
10
Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific.
i.MX31/i.MX31L Advance Information, Rev. 2.3 76 Freescale Semiconductor
Electrical Characteristics
The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD, DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD, DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers.
4.3.16
Memory Stick Host Controller (MSHC)
Figure 64, Figure 65, and Figure 66 depict the MSHC timings, and Table 48 and Table 49 list the timing parameters.
tSCLKc tSCLKwh tSCLKwl
MSHC_SCLK
tSCLKr
tSCLKf
Figure 64. MSHC_CLK Timing Diagram
tSCLKc
MSHC_SCLK
tBSsu
tBSh
MSHC_BS
tDsu MSHC_DATA (Output)
tDh
tDd MSHC_DATA (Intput)
Figure 65. Transfer Operation Timing Diagram (Serial)
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 77
Electrical Characteristics
tSCLKc
MSHC_SCLK
tBSsu
tBSh
MSHC_BS
tDsu MSHC_DATA (Output)
tDh
tDd MSHC_DATA (Intput)
Figure 66. Transfer Operation Timing Diagram (Parallel)
NOTE The Memory Stick Host Controller is designed to meet the timing requirements per Sony's Memory Stick Pro Format Specifications document. Tables in this section details the specifications requirements for parallel and serial modes, and not the i.MX31/i.MX31L timing.
Table 48. Serial Interface Timing Parameters1
Standards Signal Parameter Cycle H pulse length MSHC_SCLK L pulse length Rise time Fall time Setup time MSHC_BS Hold time Setup time MSHC_DATA Hold time Output delay time
1
Symbol Min. tSCLKc tSCLKwh tSCLKwl tSCLKr tSCLKf tBSsu tBSh tDsu tDh tDd 50 15 15 - - 5 5 5 5 - Max. - - - 10 10 - - - - 15
Unit ns ns ns ns ns ns ns ns ns ns
Timing is guaranteed for NVCC from 2.7 through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See NVCC restrictions described in Table 7, "Operating Ranges," on page 12.
i.MX31/i.MX31L Advance Information, Rev. 2.3 78 Freescale Semiconductor
Electrical Characteristics
Table 49. Parallel Interface Timing Parameters1
Standards Signal Parameter Symbol Min Cycle H pulse length MSHC_SCLK L pulse length Rise time Fall time Setup time MSHC_BS Hold time Setup time MSHC_DATA Hold time Output delay time
1
Unit Max - - - 10 10 - - - - 15 ns ns ns ns ns ns ns ns ns ns
tSCLKc tSCLKwh tSCLKwl tSCLKr tSCLKf tBSsu tBSh tDsu tDh tDd
25 5 5 - - 8 1 8 1 -
Timing is guaranteed for NVCC from 2.7 through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See NVCC restrictions described in Table 7, "Operating Ranges," on page 12.
4.3.17
Personal Computer Memory Card International Association (PCMCIA)
Figure 67 and Figure 68 depict the timings pertaining to the PCMCIA module, each of which is an example of one clock of strobe set-up time and one clock of strobe hold time. Table 50 lists the timing parameters.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 79
Electrical Characteristics
HCLK HADDR CONTROL HWDATA HREADY HRESP A[25:0] D[15:0] WAIT REG OE/WE/IORD/IOWR CE1/CE2 RW POE REG OKAY ADDR 1 DATA write 1 OKAY OKAY ADDR 1 CONTROL 1 DATA write 1
PSST
PSL
PSHT
Figure 67. Write Accesses Timing Diagram--PSHT=1, PSST=1
i.MX31/i.MX31L Advance Information, Rev. 2.3 80 Freescale Semiconductor
Electrical Characteristics
HCLK HADDR CONTROL RWDATA HREADY HRESP A[25:0] D[15:0] WAIT REG OE/WE/IORD/IOWR CE1/CE2 RW POE REG OKAY ADDR 1 OKAY OKAY ADDR 1 CONTROL 1 DATA read 1
PSST
PSL
PSHT
Figure 68. Read Accesses Timing Diagram--PSHT=1, PSST=1 Table 50. PCMCIA Write and Read Timing Parameters
Symbol PSHT PSST PSL Parameter PCMCIA strobe hold time PCMCIA strobe set up time PCMCIA strobe length Min 0 1 1 Max 63 63 128 Unit clock clock clock
4.3.18
PWM Electrical Specifications
This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 81
Electrical Characteristics
4.3.18.1
PWM Timing
Figure 69 depicts the timing of the PWM, and Table 51 lists the PWM timing characteristics.
2a System Clock 2b 3a 4a PWM Output 4b 1 3b
Figure 69. PWM Timing Table 51. PWM Output Timing Parameters
ID 1 2a 2b 3a 3b 4a 4b
1
Parameter System CLK frequency1 Clock high time Clock low time Clock fall time Clock rise time Output delay time Output setup time
Min 0 12.29 9.91 - - - 8.71
Max ipg_clk - - 0.5 0.5 9.37 -
Unit MHz ns ns ns ns ns ns
CL of PWMO = 30 pF
4.3.19
SDHC Electrical Specifications
This section describes the electrical information of the SDHC.
4.3.19.1
SDHC Timing
Figure 70 depicts the timings of the SDHC, and Table 52 lists the timing parameters.
i.MX31/i.MX31L Advance Information, Rev. 2.3 82 Freescale Semiconductor
Electrical Characteristics
SD4 SD1 CLK SD5 SD6 CMD DATA[3:0] SD7 CMD DATA[3:0] SD8 Input to SDHC Output from SDHC to card SD3 SD2
Figure 70. SDHC Timing Diagram
.
Table 52. SDHC Interface Timing Parameters
ID Parameter Symbol Min Max Unit
Card Input Clock SD1 Clock Frequency (Low Speed) Clock Frequency (SD/SDIO Full Speed) Clock Frequency (MMC Full Speed) Clock Frequency (Identification Mode) SD2 SD3 SD4 SD5 Clock Low Time Clock High Time Clock Rise Time Clock Fall Time fPP1 fPP2 fPP3 fOD
4
0 0 0 100 10 10 - -
400 25 20 400 - - 10 10
kHz MHz MHz kHz ns ns ns ns
tWL tWH tTLH tTHL
SDHC output / Card inputs CMD, DAT (Reference to CLK) SD6 SDHC output delay tODL -6.5 3 ns
SDHC input / Card outputs CMD, DAT (Reference to CLK) SD7 SD8
1
SDHC input setup SDHC input hold
tIS tIH
- -
18.5 -11.5
ns ns
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.3 V. In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0 - 25 MHz. 3 In normal data transfer mode for MMC card, clock frequency can be any value between 0 - 20 MHz. 4 In card identification mode, card clock must be 100 kHz ~ 400 kHz, voltage ranges from 2.7 to 3.3 V.
2
4.3.20
SIM Electrical Specifications
Each SIM card interface consist of a total of 12 pins (for 2 separate ports of 6 pins each. Mostly one port with 5 pins is used).
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 83
Electrical Characteristics
The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides a clock for the SIM card to use. The frequency of this clock is normally 372 times the data rate on the TX/RX pins, however SIM module can work with CLK equal to 16 times the data rate on TX/RX pins. There is no timing relationship between the clock and the data. The clock that the SIM module provides to the aim card will be used by the SIM card to recover the clock from the data much like a standard UART. All six (or 5 in case bi directional TXRX is used) of the pins for each half of the SIM module are asynchronous to each other. There are no required timing relationships between the signals in normal mode, but there are some in two specific cases: reset and power down sequences.
4.3.20.1
General Timing Requirements
Figure 71 shows the timing of the SIM module, and Figure 53 lists the timing parameters.
1/Sfreq
CLK
Sfall
Srise
Figure 71. SIM Clock Timing Diagram Table 53. SIM Timing Specification--High Drive Strength
Num 1 2 3 4
1 2
Description SIM Clock Frequency (CLK)1 SIM CLK Rise Time 2 SIM CLK Fall Time 3 SIM Input Transition Time (RX, SIMPD)
Symbol Sfreq Srise Sfall Strans
Min 0.01 - - -
Max 5 (Some new cards may reach 10) 20 20 25
Unit MHz ns ns ns
50% duty cycle clock With C = 50pF 3 With C = 50pF
4.3.20.2
4.3.20.2.1
Reset Sequence
Cards with Internal Reset
The sequence of reset for this kind of SIM Cards is as follows (see Figure 72): * After powerup, the clock signal is enabled on SGCLK (time T0) * After 200 clock cycles, RX must be high. * The card must send a response on RX acknowledging the reset between 400 and 40000 clock cycles after T0.
i.MX31/i.MX31L Advance Information, Rev. 2.3 84 Freescale Semiconductor
Electrical Characteristics
SVEN
CLK
RX 1 2
response
1 T0 400 clock cycles < 2
< 200 clock cycles < 40000 clock cycles
Figure 72. Internal-Reset Card Reset Sequence
4.3.20.2.2
Cards with Active Low Reset
The sequence of reset for this kind of card is as follows (see Figure 73): 1. After powerup, the clock signal is enabled on CLK (time T0) 2. After 200 clock cycles, RX must be high. 3. RST must remain Low for at least 40000 clock cycles after T0 (no response is to be received on RX during those 40000 clock cycles) 4. RST is set High (time T1) 5. RST must remain High for at least 40000 clock cycles after T1 and a response must be received on RX between 400 and 40000 clock cycles after T1.
SVEN
RST
CLK
RX 1 2
response
3 T0 T1
3
1 400 clock cycles < 400000 clock cycles < 2 3
< 200 clock cycles < 40000 clock cycles
Figure 73. Active-Low-Reset Card Reset Sequence
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 85
Electrical Characteristics
4.3.20.3
Power Down Sequence
Power down sequence for SIM interface is as follows: 1. SIMPD port detects the removal of the SIM Card 2. RST goes Low 3. CLK goes Low 4. TX goes Low 5. VEN goes Low Each of this steps is done in one CKIL period (usually 32 kHz). Power down can be started because of a SIM Card removal detection or launched by the processor. Figure 74 and Table 54 show the usual timing requirements for this sequence, with Fckil = CKIL frequency value.
Spd2rst
SIMPD
RST
Srst2clk CLK
Srst2dat DATA_TX
Srst2ven SVEN
Figure 74. SmartCard Interface Power Down AC Timing Table 54. Timing Requirements for Power Down Sequence
Num 1 2 3 4 Description SIM reset to SIM clock stop SIM reset to SIM TX data low SIM reset to SIM Voltage Enable Low SIM Presence Detect to SIM reset Low Symbol Srst2clk Srst2dat Srst2ven Spd2rst Min 0.9*1/FCKIL 1.8*1/FCKIL 2.7*1/FCKIL 0.9*1/FCKIL Max 0.8 1.2 1.8 25 Unit s s s ns
i.MX31/i.MX31L Advance Information, Rev. 2.3 86 Freescale Semiconductor
Electrical Characteristics
4.3.21
SJC Electrical Specifications
This section details the electrical characteristics for the SJC module. Figure 75 depicts the SJC test clock input timing. Figure 76 depicts the SJC boundary scan timing, Figure 77 depicts the SJC test access port, Figure 78 depicts the SJC TRST timing, and Table 55 lists the SJC timing parameters.
SJ1 SJ2 TCK (Input) VIH VIL SJ3 SJ3 VM SJ2 VM
Figure 75. Test Clock Input Timing Diagram
TCK (Input) VIL SJ4 Data Inputs SJ6 Data Outputs SJ7 Data Outputs SJ6 Data Outputs Output Data Valid Output Data Valid Input Data Valid SJ5
VIH
Figure 76. Boundary Scan (JTAG) Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 87
Electrical Characteristics
TCK (Input) VIL SJ8 TDI TMS (Input) SJ10 TDO (Output) SJ11 TDO (Output) SJ10 TDO (Output) Output Data Valid Output Data Valid Input Data Valid SJ9
VIH
Figure 77. Test Access Port Timing Diagram
TCK (Input) SJ13 TRST (Input)
SJ12
Figure 78. TRST Timing Diagram Table 55. SJC Timing Parameters
All Frequencies ID Parameter Min SJ1 SJ2 SJ3 SJ4 SJ5 SJ6 SJ7 SJ8 SJ9 SJ10 TCK cycle time TCK clock pulse width measured at VM2 TCK rise and fall times Boundary scan input data set-up time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid 1001 40 - 10 50 - - 10 50 - Max - - 3 - - 50 50 - - 44 ns ns ns ns ns ns ns ns ns ns Unit
i.MX31/i.MX31L Advance Information, Rev. 2.3 88 Freescale Semiconductor
Electrical Characteristics
Table 55. SJC Timing Parameters (continued)
All Frequencies ID Parameter Min SJ11 SJ12 SJ13
1
Unit Max 44 - - ns ns ns
TCK low to TDO high impedance TRST assert time TRST set-up time to TCK low
- 100 40
On cases where SDMA TAP is put in the chain, the max TCK frequency is limited by max ratio of 1:8 of SDMA core frequency to TCK limitation. This implies max frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock. 2 VM - mid point voltage
4.3.22
SSI Electrical Specifications
This section describes the electrical information of SSI. Note the following pertaining to timing information: * All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. * All timings are on AUDMUX signals when SSI is being used for data transfer. * "Tx" and "Rx" refer to the Transmit and Receive sections of the SSI. * For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx Data (for example, during AC97 mode of operation).
4.3.22.1
SSI Transmitter Timing with Internal Clock
Figure 79 depicts the SSI transmitter timing with internal clock, and Table 56 lists the timing parameters.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 89
Electrical Characteristics
SS1 SS2 AD1_TXC (Output) SS6 AD1_TXFS (bl) (Output) SS10 AD1_TXFS (wl) (Output) SS16 AD1_TXD (Output) SS43 SS42 AD1_RXD (Input) Note: SRXD Input in Synchronous mode only SS1 SS2 SS19 SS14 SS15 SS17 SS18 SS12 SS8
SS5 SS4
SS3
SS5 SS4
SS3
DAM1_T_CLK (Output) SS6 DAM1_T_FS (bl) (Output) SS10 DAM1_T_FS (wl) (Output) SS16 DAM1_TXD (Output) SS43 SS42 DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only SS19 SS14 SS15 SS17 SS18 SS12 SS8
Figure 79. SSI Transmitter with Internal Clock Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 90 Freescale Semiconductor
Electrical Characteristics
Table 56. SSI Transmitter with Internal Clock Timing Parameters
ID Internal Clock Operation SS1 SS2 SS3 SS4 SS5 SS6 SS8 SS10 SS12 SS14 SS15 SS16 SS17 SS18 SS19 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Tx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Tx/Rx) Internal FS rise time (Tx/Rx) Internal FS fall time (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high/low (Tx) CK high to STXD high impedance STXD rise/fall time 81.4 36.0 - 36.0 - - - - - - - - - - - - - 6 - 6 15.0 15.0 15.0 15.0 6 6 15.0 15.0 15.0 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min Max Unit
Synchronous Internal Clock Operation SS42 SS43 SS52 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling Loading 10.0 0 - - - 25 ns ns pF
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 91
Electrical Characteristics
4.3.22.2
SSI Receiver Timing with Internal Clock
Figure 80 depicts the SSI receiver timing with internal clock, and Table 57 lists the timing parameters.
SS1 SS5 SS2 AD1_TXC (Output) SS7 AD1_TXFS (bl) (Output) AD1_TXFS (wl) (Output) SS20 SS21 AD1_RXD (Input) SS47 SS48 AD1_RXC (Output) SS51 SS50 SS49 SS9 SS4 SS3
SS11
SS13
SS1 SS5 SS2 SS4
SS3
DAM1_T_CLK (Output) SS7 DAM1_T_FS (bl) (Output) DAM1_T_FS (wl) (Output) SS20 SS21 DAM1_RXD (Input) SS47 SS48 DAM1_R_CLK (Output) SS51 SS50 SS49 SS9
SS11
SS13
Figure 80. SSI Receiver with Internal Clock Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 92 Freescale Semiconductor
Electrical Characteristics
Table 57. SSI Receiver with Internal Clock Timing Parameters
ID Internal Clock Operation SS1 SS2 SS3 SS4 SS5 SS7 SS9 SS11 SS13 SS20 SS21 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Rx) CK high to FS (bl) high (Rx) CK high to FS (bl) low (Rx) CK high to FS (wl) high (Rx) CK high to FS (wl) low SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low 81.4 36.0 - 36.0 - - - - - 10.0 0 - - 6 - 6 15.0 15.0 15.0 15.0 - - ns ns ns ns ns ns ns ns ns ns ns Parameter Min Max Unit
Oversampling Clock Operation SS47 SS48 SS49 SS50 SS51 Oversampling clock period Oversampling clock high period Oversampling clock rise time Oversampling clock low period Oversampling clock fall time 15.04 6 - 6 - - - 3 - 3 ns ns ns ns ns
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 93
Electrical Characteristics
4.3.22.3
SSI Transmitter Timing with External Clock
Figure 81 depicts the SSI transmitter timing with external clock, and Table 58 lists the timing parameters.
SS22 SS23 SS25 SS26 SS24
AD1_TXC (Input) SS27 AD1_TXFS (bl) (Input) SS31 AD1_TXFS (wl) (Input) SS39 SS37 AD1_TXD (Output) SS45 SS44 AD1_RXD (Input) Note: SRXD Input in Synchronous mode only SS46 SS38 SS29
SS33
SS22 SS26 SS23 DAM1_T_CLK (Input) SS27 DAM1_T_FS (bl) (Input) SS31 DAM1_T_FS (wl) (Input) SS39 SS37 DAM1_TXD (Output) SS44 DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only SS46 SS45 SS38 SS29 SS25 SS24
SS33
Figure 81. SSI Transmitter with External Clock Timing Diagram
i.MX31/i.MX31L Advance Information, Rev. 2.3 94 Freescale Semiconductor
Electrical Characteristics
Table 58. SSI Transmitter with External Clock Timing Parameters
ID External Clock Operation SS22 SS23 SS24 SS25 SS26 SS27 SS29 SS31 SS33 SS37 SS38 SS39 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Tx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high/low (Tx) CK high to STXD high impedance 81.4 36.0 - 36.0 - -10.0 10.0 -10.0 10.0 - - - - - 6.0 - 6.0 15.0 - 15.0 - 15.0 15.0 15.0 ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min Max Unit
Synchronous External Clock Operation SS44 SS45 SS46 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling SRXD rise/fall time 10.0 2.0 - - - 6.0 ns ns ns
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 95
Electrical Characteristics
4.3.22.4
SSI Receiver Timing with External Clock
Figure 82 depicts the SSI receiver timing with external clock, and Table 59 lists the timing parameters.
SS22 SS26 SS23 SS25 SS24
AD1_TXC (Input) SS28 AD1_TXFS (bl) (Input) SS32 AD1_TXFS (wl) (Input) SS35 SS41 SS40 AD1_RXD (Input) SS36 SS34 SS30
SS22 SS26 SS23 SS25 SS24
DAM1_T_CLK (Input) SS28 DAM1_T_FS (bl) (Input) DAM1_T_FS (wl) (Input) SS30
SS32 SS35 SS41 SS40 SS36
SS34
DAM1_RXD (Input)
Figure 82. SSI Receiver with External Clock Timing Diagram Table 59. SSI Receiver with External Clock Timing Parameters
ID External Clock Operation SS22 SS23 SS24 SS25 SS26 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time 81.4 36.0 - 36.0 - - - 6.0 - 6.0 ns ns ns ns ns Parameter Min Max Unit
i.MX31/i.MX31L Advance Information, Rev. 2.3 96 Freescale Semiconductor
Electrical Characteristics
Table 59. SSI Receiver with External Clock Timing Parameters (continued)
ID SS28 SS30 SS32 SS34 SS35 SS36 SS40 SS41 Parameter (Rx) CK high to FS (bl) high (Rx) CK high to FS (bl) low (Rx) CK high to FS (wl) high (Rx) CK high to FS (wl) low (Tx/Rx) External FS rise time (Tx/Rx) External FS fall time SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low Min -10.0 10.0 -10.0 10.0 - - 10.0 2.0 Max 15.0 - 15.0 - 6.0 6.0 - - Unit ns ns ns ns ns ns ns ns
4.3.23
USB Electrical Specifications
This section describes the electrical information of the USBOTG port. The OTG port supports both serial and parallel interfaces. The high speed (HS) interface is supported via the ULPI (Ultra Low Pin Count Interface). Figure 83 depicts the USB ULPI timing diagram, and Table 60 lists the timing parameters.
Clock TSC Control out (stp) TSD Data out TDC Control in (dir, nxt) TDD Data in TDC THD THC
Figure 83. USB ULPI Interface Timing Diagram Table 60. USB ULPI Interface Timing Specification1
Parameter Setup time (control in, 8-bit data in) Hold time (control in, 8-bit data in) Output delay (control out, 8-bit data out)
1
Symbol
Min 6 0 -
Max - - 9
Units ns ns ns
TSC, TSD THC, THD TDC, TDD
Timing parameters are given as viewed by transceiver side.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 97
Package Information and Pinout
5
Package Information and Pinout
This section includes the following: * Pin/contact assignment information * Mechanical package drawing
5.1
MAPBGA Production Package 457 14 x 14 mm, 0.5 mm Pitch
See Figure 84 for package drawings and dimensions of the production package.
i.MX31/i.MX31L Advance Information, Rev. 2.3 98 Freescale Semiconductor
Package Information and Pinout
5.1.1
Production Package Outline Drawing
Figure 84. Production Package: Case 1581--0.5 mm Pitch
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 99
5.1.2
A 1 GND 2 GND
MAPBGA Signal Assignment
4 5 6 CSPI2 CSPI2_ USBOT _MISO SS2 G_DAT A7 STXD4 SRXD CSPI2_ CSPI2_ 5 SS0 SPI_R DY SRXD4 SCK4 STXD5 CSPI2_ SS1 SCK5 CSPI2_ MOSI SFS4 NVCC5 NVCC5 BATT_ USBOT USBOT LINE G_DAT G_DAT A6 A0 CSPI3_ NVCC5 USBOT SPI_R G_DAT DY A2 ATA_DI OW ATA_C PC_PO S0 E PC_BV PC_VS QVCC1 D2 2 PC_WA PC_CD NVCC3 IT 1 SD1_D SD1_C NVCC3 ATA0 LK USBH2 USBH2 QVCC4 _NXT _DIR CSPI1_ CSPI1_ SS2 MISO SFS3 SRXD6 NFCE D15 D9 D3 NFWE D11 NVCC1 0 QVCC4 QVCC4 QVCC4 QVCC QVCC QVCC QVCC SVCC MVCC UVCC GND TXD1 RI_DC DTR_D KEY_R KEY_R KEY_C TDI E1 CE2 OW0 OW6 OL6 RI_DT CTS2 E1 KEY_R KEY_C TMS OW4 OL2 GPIO1 GPIO1 BOOT_ GND _0 _4 MODE 0 SIMPD COMP NVCC1 NVCC1 0 ARE CKIL QVCC1 QVCC1 NVCC8 NVCC8 QVCC NVCC6 NVCC6 NVCC9 NVCC6 QVCC1 GND GND GND QVCC QVCC QVCC QVCC GND GND GND GND GND GND GND GND RESET_ IN NVCC1 CSI_H GPIO3_ SYNC 0 NVCC4 NVCC4 CSI_D8 CSI_D4 QVCC NVCC7 CSI_D1 CSI_D1 4 2 SD_D_I FPSHIF T READ LCS1 VPG1 STX0 GND 3 SFS5 7 USBOT G_DAT A3 USBOT G_DAT A5 CSPI2_ SCLK 8 9 10 RXD1 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 GND A USBOT USB_ G_NXT BYP USBOT G_DAT A1 USBOT G_DAT A4 DSR_D DSR_D RXD2 CE1 TE1 CE_CO KEY_R KEY_R KEY_C KEY_C TDO NTROL OW3 OW7 OL3 OL7 KEY_R KEY_R KEY_C KEY_C TCK OW1 OW5 OL1 OL5 DE SJC_M SVEN0 CAPTU GPIO1_ WATCH GND OD RE 6 DOG_R ST TRSTB SRX0 SCLK0 GPIO1_ GPIO1_ GND 1 5 GND GND
100 i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor
Package Information and Pinout
B
GND
GND
USBOT USB_P CTS1 G_DIR WR
DCD_D DCD_D RTS2 CE1 TE1
GND
B
C
GND
GND
USBOT USB_O DTR_D DTR_D TXD2 G_STP C CE1 TE1
KEY_R KEY_C KEY_C RTCK OW2 OL0 OL4
SRST0 GPIO1 BOOT_ BOOT_ CLKO _2 MODE1 MODE3
GND
C
D E F
GND
CSPI3_ MOSI CSPI3_ ATA_DI SCLK OR ATA_D ATA_C MACK S1
BOOT_ GND MODE2 GND DVFS0 CKIH
BOOT_ MODE4 POWER _FAIL GPIO1_ VSTBY 3 CLKSS
D E F
G PWMO PC_R W PC_RS T J PC_VS 1 K PC_CD 2 L SD1_D ATA1 M USBH2 _DATA0 N USBH2 _CLK P R T U V H PC_BV D1 PC_RE ADY SD1_D ATA3 SD1_C MD USBH2 _STP CSPI1_ SCLK
CSPI3_ MISO ATA_R ESET IOIS16
USBOT RTS1 G_CLK
DVFS1
VPG0
G
PC_P WRON SD1_D ATA2 USBH2 _DATA1 CSPI1_ SPI_R DY CSPI1_ CSPI1_ CSPI1_ SS1 MOSI SS0 STXD3 SCK3 SRXD3 STXD6 SCK6 SFS6
I2C_DA T I2C_CL CSI_VS K YNC CSI_MC CSI_D5 LK CSI_D6 CSI_D9
POR
GPIO3_ 1 CSI_PIX CLK CSI_D7
H J K L M N
NVCC3 GND
CSI_D1 1 CSI_D1 CSI_D1 CSI_D1 0 3 5 VSYNC HSYNC DRDY0 0 SD_D_ CLK CONTR AST LD0 LD6 LD10 LD15 EB1 FVCC RW FGND FUSE_V DD GND GND CS4 24 SD_D_I LCS0 O WRITE VSYNC 3 SER_R D3_REV S D3_SPL LD1 LD3 LD7 LD11 LD14 LD5 LD9 LD12 LD16
NVCC1 GND 0 NVCC1 GND 0 NVCC1 GND 0
GND GND GND
GND GND
GND GND
GND GND
NVCC7 NVCC7 NVCC7 QVCC
P R T U V W Y AA AB AC AD AE AF
SGND MGND UGND
D3_CL PAR_RS S LD4 LD2 TTM_P LD8 AD LD17 LD13 EB0
NFRB
NFWP NFCLE D13 D7 D1 A4 A6 A11 A12 A7 A9 3 A13 A3 A5 4 A2
NFALE NFRE D12 D8 D4 D0 GND GND GND GND 2
W D14 Y D10
AA D6 AB D2 AC MA10 AD GND AE GND AF GND 1
D5 NVCC2 2 IOQVD NVCC2 NVCC2 NVCC2 D 2 2 2 NVCC2 SD31 SD28 SD27 2
NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 NVCC2 M_GRA 2 2 2 2 1 1 1 NT SD23 SD21 SD18 SD16 SD13 SD9 SD7 SD5 SD3 SD2 DQM2 SDCLK
A8
A0
SDBA0 SDQS3 SD29 SD26 A24 7 SD24 A23 8 SD22 A22 9
SD25 SD20 A21 10
SDQS2 SD17 SD19 A20 11
SD15
SD12 SD11 A17 14
SD8 SD10 A16 15
SDQS0 SD4 SD6 A15 16 SD1 A14 17
SDBA1 SD30 A1 A25 5 6
SDQS1 SD14 A19 A18 12 13
SD0 DQM1 CAS SDCKE CS3 0 LBA DQM3 DQM0 SDCLK CS2 A10 RAS SDWE SDCKE CS5 1 18 19 20 21 22
ECB CS0 CS1 23
OE BCLK M_REQ GND UEST GND GND GND GND 25 GND GND 26
Figure 85. Ball Map--0.5 mm Pitch
Package Information and Pinout
Table 61 shows the device connection list for power and ground, alpha-sorted.
Table 61. 14 x 14 BGA Ground/Power ID by Ball Grid Location
GND/PWR ID FGND FUSE_VDD FVCC GND AB24 AC24 AA24 A1, A2, A25, A26, B1, B2, B25, B26, C1, C2, C24, C25, C26, D1, D25, E22, E24, F21, L12, M11, M12, M13, M14, M15, M16, N12, N13, N14, N15, N16, P12, P13, P14, P15, P16, R12, R13, R14, R15, R16, T12, T13, V17, AC2, AC26, AD1, AD2, AD24, AD25, AD26, AE1, AE2, AE24, AE25, AE26, AF1, AF2, AF25, AF26 Y6 T15 V15 G19, G21, K18 Y17, Y18, Y19, Y20 L9, M9, N11 L18, L19 E5, F6, G7 J15, J16, K15 N18, P18, R18, T18 J12, J13 J17 P9, P11, R11, T11 Y14, Y15, Y16 W7, Y7, Y8, Y9, Y10, Y11, Y12, Y13, AA6 J14, L13, L14, L15, L16, M18, U18, V10, V11, V12, V13 J10, J11, K9, L11 N9, R9, T9, U9 T14 V14 V16 T16 Ball Location
IOQVDD MGND MVCC NVCC1 NVCC2 NVCC3 NVCC4 NVCC5 NVCC6 NVCC7 NVCC8 NVCC9 NVCC10 NVCC21 NVCC22 QVCC QVCC1 QVCC4 SGND SVCC UVCC UGND
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 101
Package Information and Pinout
Table 62 shows the device connection list for signals only, alpha-sorted by signal identification.
Table 62. 14 x 14 BGA Signal ID by Ball Grid Location
Signal ID A0 A1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20 A21 A22 A23 A24 A25 A3 A4 A5 A6 A7 A8 A9 ATA_CS0 ATA_CS1 ATA_DIOR ATA_DIOW ATA_DMACK ATA_RESET BATT_LINE BCLK BOOT_MODE0 BOOT_MODE1 BOOT_MODE2 BOOT_MODE3 BOOT_MODE4 CAPTURE CAS CE_CONTROL CKIH Ball Location AD6 AF5 AF18 AC3 AD3 AD4 AF17 AF16 AF15 AF14 AF13 AF12 AB5 AF11 AF10 AF9 AF8 AF7 AF6 AE4 AA3 AF4 AB3 AE3 AD5 AF3 J6 F2 E2 H6 F1 H3 F7 AB26 F20 C21 D24 C22 D26 A22 AD20 A14 F24 Signal ID CKIL CLKO CLKSS COMPARE CONTRAST CS0 CS1 CS2 CS3 CS4 CS5 CSI_D10 CSI_D11 CSI_D12 CSI_D13 CSI_D14 CSI_D15 CSI_D4 CSI_D5 CSI_D6 CSI_D7 CSI_D8 CSI_D9 CSI_HSYNC CSI_MCLK CSI_PIXCLK CSI_VSYNC CSPI1_MISO CSPI1_MOSI CSPI1_SCLK CSPI1_SPI_RDY CSPI1_SS0 CSPI1_SS1 CSPI1_SS2 CSPI2_MISO CSPI2_MOSI CSPI2_SCLK CSPI2_SPI_RDY CSPI2_SS0 CSPI2_SS1 CSPI2_SS2 CSPI3_MISO CSPI3_MOSI Ball Location H21 C23 G26 G18 R24 AE23 AF23 AE21 AD22 AF24 AF22 M24 L26 M21 M25 M20 M26 L21 K25 L24 K26 L20 L25 K20 K24 J26 J25 P7 P2 N2 N3 P3 P1 P6 A4 E3 C7 B6 B5 C6 A5 G3 D2
i.MX31/i.MX31L Advance Information, Rev. 2.3 102 Freescale Semiconductor
Package Information and Pinout
Table 62. 14 x 14 BGA Signal ID by Ball Grid Location (continued)
Signal ID CSPI3_SCLK CSPI3_SPI_RDY CTS1 CTS2 D0 D1 D10 D11 D12 D13 D14 D15 D2 D3 D3_CLS D3_REV D3_SPL D4 D5 D6 D7 D8 D9 DCD_DCE1 DCD_DTE1 DE DQM0 DQM1 DQM2 DQM3 DRDY0 DSR_DCE1 DSR_DTE1 DTR_DCE1 DTR_DCE2 DTR_DTE1 DVFS0 DVFS1 EB0 EB1 ECB FPSHIFT GPIO1_0 GPIO1_1 GPIO1_2 Ball Location E1 G6 B11 G13 AB2 Y3 Y1 U7 W2 V3 W1 U6 AB1 W6 R20 T26 U25 AA2 V7 AA1 W3 Y2 V6 B12 B13 C18 AE19 AD19 AA20 AE18 N26 A11 A12 C11 F12 C12 E25 G24 W21 Y24 AD23 N21 F18 B23 C20 Signal ID GPIO1_3 GPIO1_4 GPIO1_5 (PWR RDY) GPIO1_6 GPIO3_0 GPIO3_1 HSYNC I2C_CLK I2C_DAT IOIS16 KEY_COL0 KEY_COL1 KEY_COL2 KEY_COL3 KEY_COL4 KEY_COL5 KEY_COL6 KEY_COL7 KEY_ROW0 KEY_ROW1 KEY_ROW2 KEY_ROW3 KEY_ROW4 KEY_ROW5 KEY_ROW6 KEY_ROW7 L2PG LBA LCS0 LCS1 LD0 LD1 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD2 LD3 LD4 LD5 LD6 Ball Location F25 F19 B24 A23 K21 H26 N25 J24 H25 J3 C15 B17 G15 A17 C16 B18 F15 A18 F13 B15 C14 A15 G14 B16 F14 A16 See VPG1 AE22 P26 P21 T24 U26 V24 Y25 Y26 V21 AA25 W24 AA26 V20 T21 V25 T20 V26 U24
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 103
Package Information and Pinout
Table 62. 14 x 14 BGA Signal ID by Ball Grid Location (continued)
Signal ID LD7 LD8 LD9 M_GRANT M_REQUEST MA10 MCUPG NFALE NFCE NFCLE NFRB NFRE NFWE NFWP OE PAR_RS PC_BVD1 PC_BVD2 PC_CD1 PC_CD2 PC_POE PC_PWRON PC_READY PC_RST PC_RW PC_VS1 PC_VS2 PC_WAIT POR POWER_FAIL PWMO RAS READ RESET_IN RI_DCE1 RI_DTE1 RTCK RTS1 RTS2 RW RXD1 RXD2 SCK3 SCK4 SCK5 Ball Location W25 U21 W26 Y21 AC25 AC1 See VPG0 V1 T6 U3 U1 V2 T7 U2 AB25 R21 H2 K6 L7 K1 J7 K3 J2 H1 G2 J1 K7 L6 H24 E26 G1 AF19 P20 J21 F11 G12 C17 G11 B14 AB22 A10 A13 R2 C4 D3 Signal ID SCK6 SCLK0 SD_D_CLK SD_D_I SD_D_IO SD0 SD1 SD1_CLK SD1_CMD SD1_DATA0 SD1_DATA1 SD1_DATA2 SD1_DATA3 SD10 SD11 SD12 SD13 SD14 SD15 SD16 SD17 SD18 SD19 SD2 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD3 SD30 SD31 SD4 SD5 SD6 SD7 SD8 SD9 SDBA0 SDBA1 Ball Location T2 B22 P24 N20 P25 AD18 AE17 M7 L2 M6 L1 L3 K2 AE15 AE14 AD14 AA14 AE13 AD13 AA13 AD12 AA12 AE11 AA19 AE10 AA11 AE9 AA10 AE8 AD10 AE7 AA9 AA8 AD9 AA18 AE6 AA7 AD17 AA17 AE16 AA16 AD15 AA15 AD7 AE5
i.MX31/i.MX31L Advance Information, Rev. 2.3 104 Freescale Semiconductor
Product Documentation
Table 62. 14 x 14 BGA Signal ID by Ball Grid Location (continued)
Signal ID SDCKE0 SDCKE1 SDCLK SDCLK SDQS0 SDQS1 SDQS2 SDQS3 SDWE SER_RS SFS3 SFS4 SFS5 SFS6 SIMPD0 SJC_MOD SRST0 SRX0 SRXD3 SRXD4 SRXD5 SRXD6 STX0 STXD3 STXD4 STXD5 STXD6 SVEN0 TCK TDI TDO TMS Ball Location AD21 AF21 AA21 AE20 AD16 AE12 AD11 AD8 AF20 T25 R6 F3 A3 T3 G17 A20 C19 B21 R3 C3 B4 R7 F17 R1 B3 C5 T1 A21 B19 F16 A19 G16 Signal ID TRSTB TTM_PAD TXD1 TXD2 USB_BYP USB_OC USB_PWR USBH2_CLK USBH2_DATA0 USBH2_DATA1 USBH2_DIR USBH2_NXT USBH2_STP USBOTG_CLK USBOTG_DATA0 USBOTG_DATA1 USBOTG_DATA2 USBOTG_DATA3 USBOTG_DATA4 USBOTG_DATA5 USBOTG_DATA6 USBOTG_DATA7 USBOTG_DIR USBOTG_NXT USBOTG_STP VPG0 VPG1 VSTBY VSYNC0 VSYNC3 WATCHDOG_RST WRITE Ball Location B20 U20 F10 C13 A9 C10 B10 N1 M1 M3 N7 N6 M2 G10 F9 B8 G9 A7 C8 B7 F8 A6 B9 A8 C9 G25 J20 F26 N24 R26 A24 R25
6
Product Documentation
This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com. All related product documentation for the i.MX31 and i.MX31L is located at http://www.freescale.com\imx.
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 105
Product Documentation
6.1
Revision History
Table 63 summarizes revisions to this document since the release of Rev. 2.1.
Table 63. Revision History
Rev 2.2 2.2 2.2 2.2 2.2 Location Was Figure 3, "Power-Up Sequence Option 2," on page 16 Revision Deleted Figure 3, Power-Up Sequence, Option 2 Removed "Option 1" from Figure 2.
Table 29, "WEIM Bus Timing Parameters," Changed WEIM13/14 min/max parameter values. on page 35 Table 27, "DPLL Specifications," on page 31 Table 52, "SDHC Interface Timing Parameters," on page 83 Table 7, "Operating Ranges," on page 12 Added PLL output frequency range parameters. Revised maximum parameter values for SD7/8. Changed the following parameter values: * Core operating voltage * PLL/FPM operating voltage * Modified footnotes 2 and 6.
2.3 2.3
Fig 67 Write Access Timing and Figure 68 Changed RD/WR signal name to RW and inverted the RW waveforms. Read Access Timing Diagrams * Figure 19, "CSPI Master Mode Timing Diagram," on page 30 and Figure 20, "CSPI Slave Mode Timing Diagram," on page 30 * Table 26, "CSPI Interface Timing Parameters," on page 30 Table 7, "Operating Ranges," on page 12 * CSPI Timing Diagrams redrawn to reference the proper clock edge for data. * CSPI Interface Timing Parameters table's signal name descriptions changed to match timing diagrams. * CSPI parameter CS9 changed from 5 to 6 ns. * CS11 minimum value removed and footnote added. Added statement to Table 7 Operation Conditions footnote 3 concerning Real-Time Clock functionality in State-Retention Mode.
2.3 2.3 2.3 2.3
Table 30, "DDR/SDR SDRAM Read Cycle DDR/SDR Read cycle Timing: SD9 changed from 1.2 to 1.8 ns. Timing Parameters," on page 40 Table 6, "Thermal Resistance Added table to data sheet. Data--14 x 14 mm Package," on page 11 Throughout Document Minor changes throughout document, including: * Change heading name from Power Specifications to Supply Current Specifications. * Changed reference to Chapter 4 of the reference manual from Signal Description Pin Assignment table, to Multiplexing table. * Relocated Fusebox Supply Current Parameters table.
i.MX31/i.MX31L Advance Information, Rev. 2.3 106 Freescale Semiconductor
Product Documentation
i.MX31/i.MX31L Advance Information, Rev. 2.3 Freescale Semiconductor 107
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Document Number: MCIMX31 Rev. 2.3 03/2007

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